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bab6f62d2f5697c0cbac7da6a6eb2bef2248df8f
vllm-omni
/
tests
/
diffusion
/
models
/
wan2_2
T
History
Ayush Agarwal
dc8a9e2f17
[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (
#2749
)
...
Signed-off-by: ayushag <
ayushag@nvidia.com
>
2026-04-20 21:21:43 +08:00
..
__init__.py
[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (
#2749
)
2026-04-20 21:21:43 +08:00
conftest.py
[Refactor] refactor wan2.2 diffuse && add ut (
#2672
)
2026-04-17 20:13:49 +08:00
test_wan22_i2v_pipeline.py
[Refactor] refactor wan2.2 diffuse && add ut (
#2672
)
2026-04-17 20:13:49 +08:00
test_wan22_pipeline_diffuse.py
[Refactor] refactor wan2.2 diffuse && add ut (
#2672
)
2026-04-17 20:13:49 +08:00
test_wan22_pipeline_helpers.py
[Refactor] refactor wan2.2 diffuse && add ut (
#2672
)
2026-04-17 20:13:49 +08:00
test_wan22_ti2v_pipeline.py
[Refactor] refactor wan2.2 diffuse && add ut (
#2672
)
2026-04-17 20:13:49 +08:00
test_wan22_vace_pipeline.py
[Refactor] refactor wan2.2 diffuse && add ut (
#2672
)
2026-04-17 20:13:49 +08:00
