Ayush Agarwal dc8a9e2f17 [Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (#2749) ...

Signed-off-by: ayushag <ayushag@nvidia.com>

2026-04-20 21:21:43 +08:00

..

bagel

[CI] Restructure vLLM-Omni Test Layout, Fixture Scope, and Support Modules (#2620)

2026-04-20 14:23:42 +08:00

dmd2

[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (#2749)

2026-04-20 21:21:43 +08:00

flux

[AutoRound] Add offline quantized W4A16 model support (#1777)

2026-04-02 13:57:53 +08:00

flux2

[CI] Restructure vLLM-Omni Test Layout, Fixture Scope, and Support Modules (#2620)

2026-04-20 14:23:42 +08:00

glm_image

[CI] Restructure vLLM-Omni Test Layout, Fixture Scope, and Support Modules (#2620)

2026-04-20 14:23:42 +08:00

hunyuan_image3

Feat/Add HunyuanImage-3.0-Instruct ar part support: (#2713)

2026-04-16 23:15:25 +08:00

ltx2

[Model] Add HSDP support for LTX-2 (#2899)

2026-04-20 18:51:16 +08:00

nextstep_1_1

[CI]: Add core_model and cpu markers for L1 use case. (#1709)

2026-03-10 17:39:37 +08:00

qwen_image

[Bugfix] Limit Qwen-Image-Edit-2511 input image count (#2840)

2026-04-17 20:07:30 +08:00

t5_encoder

[Feat] Support T5 Tensor Parallelism (#1881)

2026-03-20 08:49:01 +08:00

wan2_2

[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (#2749)

2026-04-20 21:21:43 +08:00

z_image

[CI]: Add core_model and cpu markers for L1 use case. (#1709)

2026-03-10 17:39:37 +08:00