Hongsheng Liu
fd0e92183a
Signed-off-by: hsliuustc0106 <liuhongsheng4@huawei.com> Signed-off-by: Hongsheng Liu <liuhongsheng4@huawei.com>
19 lines
1020 B
Markdown
19 lines
1020 B
Markdown
# Archived module design pages
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This directory preserves module-design pages that predate the structure
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proposed in [issue #5137](https://github.com/vllm-project/vllm-omni/issues/5137).
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They are historical snapshots, not active architectural contracts, and are
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intentionally excluded from the documentation navigation.
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| Archived page | Active destination |
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| --- | --- |
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| [AR Module](ar_module.md) | [Autoregressive Runtime](../ar_runtime.md) |
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| [AsyncOmni Architecture](async_omni_architecture.md) | [Engine Orchestration](../engine_orchestration.md) and [Stage Runtime](../stage_runtime.md) |
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| [DiT Module](dit_module.md) | [Diffusion module overview](../diffusion/index.md) |
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| [Entrypoint Module](entrypoint_module.md) | [Entrypoints and Serving Boundaries](../entrypoints.md) |
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Do not update these pages with current design guidance. Move still-useful
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material into the active destination and review it against current code and
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tests instead. No compatibility redirect pages are provided at the former
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paths.
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