 andyluo7
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bbf77cce69
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[CI][ROCm] Add non-blocking entrypoint GPU coverage (#7398)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-16 07:25:56 +08:00 |
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andyluo7
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92715f3f7b
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[CI][ROCm] Add non-blocking engine and model executor GPU coverage (#7397)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-15 13:24:34 +08:00 |
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andyluo7
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58adeec05f
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[CI/Build] Add experimental AMD MI300 nightly lane (#6978)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-14 12:02:28 +08:00 |
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andyluo7andHongsheng Liu
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dff8f8f4cf
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[CI][ROCm] Align AMD image with vLLM 0.29 (#7395)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-09-11 17:41:45 +08:00 |
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andyluo7
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d8d4062547
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[CI] Isolate layerwise offload memory measurements (#6938)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-10 17:58:24 +08:00 |
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andyluo7
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3d71a2b3ad
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[CI/Build] Stabilize LTX2 vocoder autocast test on ROCm (#7336)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-10 10:09:39 +08:00 |
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andyluo7
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b9932aa17b
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[CI/Build][ROCm] Normalize SenseNova paged-decode hardware markers (#6935)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-09 07:32:38 -07:00 |
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andyluo7andHongsheng Liu
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c94cf4ddde
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[CI][ROCm] Match CUDA/NPU L2/L3 label routing (#6966)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-09-09 13:47:15 +00:00 |
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andyluo7
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e0d0879794
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[Bugfix][Magi2] Allow import without an active Triton driver (#7239)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-08 22:48:08 -07:00 |
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andyluo7
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de1b0708bd
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[CI][ROCm] Route LTX2 Ulysses parity to two-GPU lane (#7234)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-08 22:59:37 +08:00 |
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andyluo7andwangyu
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b58ff5cb8b
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[CI/Build] Wait for duplex reaper recovery in retry test (#7225)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: wangyu <53896905+yenuo26@users.noreply.github.com>
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2026-09-08 17:10:51 +08:00 |
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andyluo7andHongsheng Liu
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477083a103
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[CI][ROCm] Fix deterministic AMD L3 blockers (#6884)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-09-01 22:53:00 +08:00 |
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