 andyluo7
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c9bee166fb
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ci: route AR paged attention tests to GPU lanes (#8346)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-10-04 23:13:21 +13:00 |
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andyluo7
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3ab726c126
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test: bound CPU vocoder reference threads (#8347)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-10-04 19:19:22 +13:00 |
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andyluo7
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b171731c81
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fix: preserve CosyVoice full payload and live conditioning (#8343)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-10-04 16:03:27 +13:00 |
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andyluo7
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09d704907f
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fix: preserve Torch seeded sampling on ROCm (#8341)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-10-04 16:03:21 +13:00 |
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andyluo7
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c150600896
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[Bugfix] Route MOSS reference attention through ROCm FlashAttention (#8463)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-10-04 16:02:22 +13:00 |
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andyluo7
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ee8fdab1dc
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[CI/Build] Fix MOSS CPU tests on ROCm workers (#8447)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-10-03 09:13:51 +08:00 |
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andyluo7
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53c7340668
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test: measure offload memory inside diffusion workers (#8189)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-10-02 14:07:20 +08:00 |
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andyluo7
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bbee488da3
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fix: repair ROCm test routing, CPU timeouts, and Breeze autotuning (#8342)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-10-02 07:36:41 +08:00 |
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andyluo7
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f145f66c82
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test: define Wan fused BF16 parity budget (#8188)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-29 22:43:14 +08:00 |
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andyluo7andwangyu
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36b74f99f6
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test: keep Hunyuan LoRA CPU path on native linear (#8166)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: wangyu <53896905+yenuo26@users.noreply.github.com>
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2026-09-28 04:33:40 +00:00 |
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andyluo7andAlicia
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b63e35ab4f
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ci: extend AMD Z-Image cold-start timeout (#8195)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Alicia <115451386+congw729@users.noreply.github.com>
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2026-09-27 06:11:05 +00:00 |
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andyluo7
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ad025defe6
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[CI][Diffusion] Restore Krea2 model type marker (#8164)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-26 12:55:06 +08:00 |
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andyluo7
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9b08ac8203
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[Bugfix][Diffusion] Clean up inline worker lifecycle (#7986)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-24 21:43:25 +08:00 |
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andyluo7
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1586c41ae4
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[CI][ROCm] Shorten the blocking CosyVoice test path (#7748)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-21 18:34:40 -07:00 |
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andyluo7
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fa422a3f44
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[CI/Build][ROCm] Cache AMD test images in registry (#7712)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-20 09:51:14 +08:00 |
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andyluo7
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232dbc82f8
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[CI/Build] Restrict ERNIE fused RoPE tests to NVIDIA CUDA (#7771)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-19 13:23:50 +08:00 |
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1c7476ec19
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[CI/Build][ROCm] Stabilize shared AMD test lanes (#7706)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Signed-off-by: haic0 <haic0@users.noreply.github.com>
Co-authored-by: haic0 <haic0@users.noreply.github.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-18 11:13:07 +08:00 |
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andyluo7
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bbf77cce69
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[CI][ROCm] Add non-blocking entrypoint GPU coverage (#7398)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-16 07:25:56 +08:00 |
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andyluo7
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92715f3f7b
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[CI][ROCm] Add non-blocking engine and model executor GPU coverage (#7397)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-15 13:24:34 +08:00 |
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andyluo7
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58adeec05f
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[CI/Build] Add experimental AMD MI300 nightly lane (#6978)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-14 12:02:28 +08:00 |
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andyluo7andHongsheng Liu
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dff8f8f4cf
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[CI][ROCm] Align AMD image with vLLM 0.29 (#7395)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-09-11 17:41:45 +08:00 |
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andyluo7
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d8d4062547
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[CI] Isolate layerwise offload memory measurements (#6938)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-10 17:58:24 +08:00 |
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andyluo7
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3d71a2b3ad
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[CI/Build] Stabilize LTX2 vocoder autocast test on ROCm (#7336)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-10 10:09:39 +08:00 |
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andyluo7
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b9932aa17b
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[CI/Build][ROCm] Normalize SenseNova paged-decode hardware markers (#6935)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-09 07:32:38 -07:00 |
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andyluo7andHongsheng Liu
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c94cf4ddde
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[CI][ROCm] Match CUDA/NPU L2/L3 label routing (#6966)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-09-09 13:47:15 +00:00 |
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andyluo7
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e0d0879794
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[Bugfix][Magi2] Allow import without an active Triton driver (#7239)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-08 22:48:08 -07:00 |
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andyluo7
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de1b0708bd
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[CI][ROCm] Route LTX2 Ulysses parity to two-GPU lane (#7234)
Signed-off-by: andyluo7 <andy.luo@amd.com>
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2026-09-08 22:59:37 +08:00 |
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andyluo7andwangyu
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b58ff5cb8b
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[CI/Build] Wait for duplex reaper recovery in retry test (#7225)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: wangyu <53896905+yenuo26@users.noreply.github.com>
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2026-09-08 17:10:51 +08:00 |
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andyluo7andHongsheng Liu
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477083a103
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[CI][ROCm] Fix deterministic AMD L3 blockers (#6884)
Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-09-01 22:53:00 +08:00 |
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