[Docs] Remove stale DLO validation results
Signed-off-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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@@ -56,9 +56,9 @@ ordinary-loader compatibility path: DLO can consume the resulting TP-local
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tensors. Direct checkpoint mmap still does not cover TP, but the Phase B cache
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can share each final TP coordinate among equivalent processes.
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The compatibility matrix below describes the current implementation. The
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unit-level guards are covered, but not every parallelism combination has a
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full model-and-hardware end-to-end test.
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The compatibility matrix below defines the current implementation boundary.
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Hardware and performance qualification is tracked separately from this
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long-lived design contract.
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## Architecture
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@@ -446,8 +446,8 @@ This mode means:
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|---|---|---|
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| **DP** | Supported primary path. DLO shards host weights across the DP group and can run DP multi-concurrency. | Supported rank-local path. Compatible TP1 replicas can share checkpoint pages; the optional runtime cache shares equivalent final layouts while excluding DP rank from its identity. CUDA workers may register the complete final mapping for direct H2D. |
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| **SP** | Supported in the implementation. With DP=1, DLO uses the SP group for host-weight sharding; SP still shards sequence/activation work. | SP remains active without a DLO weight collective. Runtime-cache v1 excludes SP rank and includes conservative SP implementation/world-size guards. Registered transfer does not remove ordinary SP activation/attention collectives. |
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| **TP > 1** | Outside the Phase A direct-mmap scope. The loader preserves TP-local layouts and DLO may apply DP/SP host sharding to ordinary runtime tensors. | The ordinary TP-aware loader produces rank-local tensors. Runtime-cache v1 creates one entry per TP coordinate, shareable by equivalent DP/SP processes. Registering those final mappings removes staging-driven TP skew but does not remove ordinary TP collectives. |
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| **HSDP** | Rejected. HSDP has already sharded parameters, so DLO AllGather would double-shard them. | Accepted by configuration. HSDP owns parameter sharding and its own gathers; DLO only stages rank-local parameters. End-to-end coverage is limited. |
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| **TP > 1** | Outside the Phase A direct-mmap scope. The loader preserves TP-local layouts and DLO may apply DP/SP host sharding to ordinary runtime tensors. | The ordinary TP-aware loader produces rank-local tensors. Runtime-cache v1 creates one entry per TP coordinate, shareable by equivalent DP/SP processes. Registering those final mappings avoids the recurrent staging copy but does not remove ordinary TP collectives. |
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| **HSDP** | Rejected. HSDP has already sharded parameters, so DLO AllGather would double-shard them. | Accepted only with ordinary-loader rank-local tensors. HSDP owns parameter sharding and its own gathers; runtime-cache v1 rejects HSDP/DTensor layouts. |
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### Combined dimensions
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@@ -487,183 +487,19 @@ configurations, HSDP/DTensor, expert parallelism, CFG parallelism, PP,
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non-contiguous tensors, and
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tied/shared storage.
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## Validation coverage
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## Validation status
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Current source-level validation includes:
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- HSDP + DLO + AllGather rejection;
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- HSDP + DLO without AllGather acceptance at configuration level;
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- loader preflight fallback for TP, HSDP, online quantization, unknown custom
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loaders, missing keys, and shape/dtype mismatches;
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- ordinary-loader fallback for per-tensor online FP8 linears followed by DLO
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sharding of finalized weights and scales;
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- exact loader-to-backend plan transfer and ordinary-loader fallback;
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- rank-local mmap source retention, bounded two-slot staging, and adapter
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transforms without parameter-side flags;
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- runtime-cache content identity, sharded atomic publication, concurrent
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writer election, corruption rebuild, lock timeout, and fail-closed layout
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rejection;
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- loader ordering through final post-load mutation and DLO remapping without
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rerunning post-load hooks;
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- all-or-nothing page-aligned registration, budget rejection, partial-failure
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rollback, direct-copy staging bypass, and explicit shutdown cleanup;
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- resident-layer requests requiring no-AllGather;
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- DP request-wave validation for denoising-step compatibility;
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- sharding, double-buffer, AllGather-size, and heterogeneous-block regression
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tests.
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### B300 parallel-topology smoke matrix
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A four-GPU B300 smoke test covered MiniMax-H3 FL2VA with the same prompt, seed,
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CUDNN attention backend, 256x256 output, two denoising steps, and
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`dlo_resident_layers=0`. The TP2 rows used DiT DP2xTP2 with the text encoder and
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VAEs at TP1. They validate the ordinary-loader fallback only, not direct mmap
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or shared-mmap host-memory savings.
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| Configuration | Result | Warm E2E | Peak device memory | Host PSS |
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|---|---:|---:|---:|---:|
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| DP4xTP1 AllGather | Passed, 4 concurrent requests | 2.87 s / 4 requests | 13.84 GiB | 211.99 GiB |
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| DP4xTP1 no-AllGather | Passed, 1 request | 15.02 s | 13.23 GiB | 187.77 GiB |
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| DP2xTP2 AllGather | Passed, 2 concurrent requests | 4.16 s / 2 requests | 12.50 GiB | 211.97 GiB |
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| DP2xTP2 no-AllGather | Passed, 1 request | 3.51 s | 11.88 GiB | 314.01 GiB |
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Within each topology, the AllGather and no-AllGather video and audio outputs
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were byte-identical. All four runs completed without an `ERROR` or traceback
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and released their device allocations. For DP4xTP1, no-AllGather direct mmap
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reduced total PSS by 24.22 GiB (11.4%) and `Private_Dirty` from 211.33 to
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125.32 GiB (40.7%) relative to AllGather. For DP2xTP2, preflight selected the
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ordinary loader as designed; no-AllGather PSS was 314.01 GiB, about 48% above
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AllGather, because DP replicas did not share checkpoint-backed runtime
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weights. This is a functional and memory smoke test, not a production-quality
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performance or output-quality benchmark.
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### Host-memory measurement
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A two-worker MiniMax-H3 FL2VA measurement on one L20X node compared the
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ordinary-loader fallback with direct mmap. Both runs used
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DP=2, TP=1, no DLO AllGather, BF16 weights, two denoising steps, and a
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256x256 four-second request. The ordinary-loader workers were sampled after
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initialization. The mmap workers were sampled after one completed request, so
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the checkpoint working set had been faulted into the page cache; this is the
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more conservative point for mmap.
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The values below come from `/proc/<worker>/smaps_rollup` and include the whole
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worker, not only the DiT. The stable rank-to-rank difference comes from other
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pipeline components, so each worker should be compared with the same worker in
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the other storage mode.
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| Worker | Ordinary RSS | mmap RSS | Ordinary PSS | mmap PSS | PSS reduction |
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|---|---:|---:|---:|---:|---:|
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| DP worker 0 | 168.27 GiB | 132.76 GiB | 167.84 GiB | 101.43 GiB | 66.40 GiB |
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| DP worker 1 | 116.19 GiB | 79.97 GiB | 115.73 GiB | 48.64 GiB | 67.09 GiB |
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| **Two-worker total** | — | — | **283.56 GiB** | **150.08 GiB** | **133.48 GiB (47.1%)** |
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The direct-mmap workers each reported 62.45 GiB `Shared_Clean` but only
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31.20 GiB `Pss_File`, which is the proportional charge expected when the same
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resident checkpoint pages are mapped by two workers. `Private_Dirty` also fell
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from 167.53 to 70.24 GiB for worker 0 and from 115.40 to 17.44 GiB for worker
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1, a reduction of about 97–98 GiB per worker. RSS understates this benefit
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because it counts a shared physical page in every process that maps it; summed
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PSS is the appropriate node-memory comparison.
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### L20X runtime-cache smoke matrix
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Phase B was also exercised on four L20X GPUs in one NVLink domain with
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MiniMax-H3 FL2VA, CUDNN attention, eager execution, 256x256 four-second
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outputs, two denoising steps, `dlo_resident_layers=0`, text-encoder TP1, and
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VAE TP1. This is a functional, memory, and profiler smoke test rather than a
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production-quality performance benchmark. Host values below are node-wide
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maxima during request waves from descendant-process `smaps_rollup`; they do
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not represent the private startup peak. HBM is the engine-reported request
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peak because sampled `nvidia-smi` data can miss short-lived allocations.
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One internal DP2xTP2 engine compared the three host-storage/transfer choices.
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Each measured wave contained two requests. NVLink TX is the physical per-link
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counter delta summed across the four GPUs; RX had the same value and is not
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added again here.
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| Mode | Two-request wave | Throughput | Host PSS | `Private_Dirty` | Engine peak HBM | NVLink TX / wave |
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|---|---:|---:|---:|---:|---:|---:|
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| AllGather, ordinary loader | 3.41 s | 0.587 req/s | 210.70 GiB | 209.72 GiB | 12,498 MB | 73.37 GiB |
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| no-AllGather, private loader weights | 6.96 s | 0.287 req/s | 312.56 GiB | 311.56 GiB | 11,882 MB | 19.78 GiB |
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| no-AllGather, runtime cache (cold publish) | 18.94 s | 0.106 req/s | 178.71 GiB | 116.00 GiB | 11,882 MB | 19.78 GiB |
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| no-AllGather, runtime cache (warm reuse) | 24.23 s | 0.083 req/s | 178.29 GiB | 115.58 GiB | 11,882 MB | 19.78 GiB |
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The no-AllGather cache preserved the no-AllGather NVLink traffic and HBM
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footprint while reducing node PSS by about 134 GiB relative to private loader
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weights. Cold and warm labels describe cache publication or reuse during
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initialization; both request phases ran after initialization. A warm hit still
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performed ordinary loading and full content hashing, so it was not a startup
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fast path. All measured no-AllGather private/cache outputs were byte-identical
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for matching seeds.
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The deployment shape targeted by the cache was tested separately as two
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independent DP1xTP2 engines on the same node. Both engines mapped the same two
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TP-coordinate entries, including the same file device/inode tuples; the cache
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occupied 66,281,995,903 bytes. A start barrier kept all four measured requests
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ahead of profiling.
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| Storage | Mean request latency, engines A / B | Combined throughput | Host PSS | `Private_Dirty` | Engine peak HBM |
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|---|---:|---:|---:|---:|---:|
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| Private loader weights | 3.50 / 3.60 s | 0.463 req/s | 366.20 GiB | 365.22 GiB | 11,882 MB |
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| Shared runtime cache | 8.96 / 12.30 s | 0.142 req/s | 232.23 GiB | 169.52 GiB | 11,882 MB |
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The shared cache reduced request-time PSS by 133.97 GiB (36.6%) and
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`Private_Dirty` by 195.70 GiB (53.6%), but reduced combined throughput by
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69.3% in this host-contention smoke. Across one profiled request per engine,
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aggregate GPU compute was unchanged (1.359 versus 1.357 seconds) and H2D
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payload was exactly 264.24 GiB in both modes. Aggregate CPU `aten::copy_` time
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rose from 3.75 to 32.49 seconds, while communication-kernel time rose from
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3.56 to 5.80 seconds as TP ranks waited on skewed staging. These durations are
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summed across ranks and can overlap; they identify the mechanism, not wall
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time. Matching private/cache outputs were byte-identical.
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The result confirms that zero-budget runtime-cache staging is a host-capacity
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option, not a latency-neutral replacement for private pinned weights. Broader
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SP, model, platform, and production-quality validation remains tracked in
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[issue #6231](https://github.com/vllm-project/vllm-omni/issues/6231). The
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historical B300 rows above predate the runtime cache and must not be treated as
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Phase B memory validation.
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### L20X registered-runtime-cache smoke
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The read-only registered path was then tested with the same MiniMax-H3
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workload. These are functional and mechanism-validation measurements, not a
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production benchmark. The TP1 pair used one request per wave. Both modes moved
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exactly 121.86 GiB H2D in the profiled request and produced byte-identical video
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and audio for both measured seeds.
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| TP1 no-AllGather mode | Mean wave | Throughput | Request-time host PSS | `Private_Dirty` | Engine peak HBM | CPU `aten::copy_` | GPU compute |
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|---|---:|---:|---:|---:|---:|---:|---:|
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| Checkpoint mmap + bounded staging | 33.87 s | 0.0295 req/s | 133.65 GiB | 71.16 GiB | 13,226 MB | 21.91 s | 419.28 ms |
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| Final runtime cache + registered direct H2D | 4.88 s | 0.2055 req/s | 129.41 GiB | 66.93 GiB | 13,226 MB | 1.64 s | 419.05 ms |
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Registration covered 61.73 GiB in 13 page-aligned ranges. Mean wave latency
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fell by 85.6% and throughput increased 6.94x. GPU compute and H2D payload were
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unchanged, identifying recurrent host transform/packing as the removed work.
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The direct path issued 2,425 H2D events versus 1,945 for packed staging, but
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that launch increase was much smaller than the eliminated CPU cost.
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Two independent TP2 engines also registered the same two TP-coordinate cache
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entries across four workers. Compared with the zero-budget cache, mean wave
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latency improved from 9.21/12.55 seconds to 3.80/3.86 seconds for engines A/B;
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the private-loader reference was 3.61/3.72 seconds. Registered request-time
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host PSS was 224.26 GiB versus 232.23 GiB staged and 366.20 GiB private.
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Aggregate CPU `aten::copy_` time was 3.83 seconds registered, 32.49 seconds
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staged, and 3.75 seconds private; aggregate GPU compute and the 264.24 GiB H2D
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payload were effectively unchanged. Ordinary TP communication remained, but
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the extra wait caused by staging-driven rank skew largely disappeared.
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All workers explicitly unregistered before releasing their mappings, the
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system's acquired-minus-released pin counter returned to its pre-run value,
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and every GPU allocation was released. Cold runtime-cache publication remained
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expensive because it still performs ordinary loading and multiple full-content
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passes; that startup problem is outside the registered transfer scope.
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Historical test counts and hardware measurements are intentionally not kept
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in this design document because they can drift as the implementation changes.
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Revalidation must run against the final commit and publish commit-pinned
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artifacts before making hardware or performance claims. Track that work in
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[issue #6231](https://github.com/vllm-project/vllm-omni/issues/6231).
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## Recommendations
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- Use **DP + DLO AllGather** for the supported throughput and host-memory
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scaling path.
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- Use **DP + DLO AllGather** when ranks already execute the same block path in
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lockstep and belong to the same fast P2P domain. It shards persistent host
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weights across that group.
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- Use **SP + DLO AllGather** for long-sequence workloads when DP concurrency is
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not the goal.
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- Use **no-AllGather** when independent replica execution is required. TP1
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@@ -674,5 +510,5 @@ passes; that startup problem is outside the registered transfer scope.
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registration budget large enough for the complete final layout when
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recurrent staging cost is unacceptable; leave it at zero when page-locking
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that layout is not operationally acceptable.
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- Prefer **HSDP alone** for production HSDP deployments until the combined
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HSDP + DLO no-AllGather path has broader end-to-end coverage.
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- Do not combine HSDP with DLO AllGather or runtime-cache v1. HSDP with
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no-AllGather remains an ordinary-loader rank-local path.
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@@ -7,7 +7,7 @@ no-AllGather path can optionally share node-local runtime weights through mmap.
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See the [DLO component architecture](../../../design/feature/offloader/distributed_layerwise_offload.md#architecture)
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for ownership and lifecycle coordination, and the remaining feature design for
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loader contracts, compatibility details, failure handling, and benchmarks.
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loader contracts, compatibility details, and failure handling.
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## Choose a mode
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@@ -92,12 +92,11 @@ SP model collectives still synchronize ranks within each engine.
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until their runtime layouts are validated.
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- Runtime-cache v1 rejects quantized, non-contiguous, aliased/tied, device-only,
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HSDP, expert-parallel, CFG-parallel, and PP layouts.
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- HSDP plus DLO AllGather is unsupported. HSDP without AllGather has limited
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end-to-end validation.
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- The runtime cache lowers steady-state host PSS, not startup peak: each worker
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still performs ordinary loading and full content validation.
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- Skip-load-on-hit, cache eviction, cross-node sharing, and broader SP hardware
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validation remain follow-up work in
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- HSDP plus DLO AllGather is unsupported, and runtime-cache v1 rejects HSDP.
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- The runtime cache changes steady-state host backing, not startup loading:
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each worker still performs ordinary loading and full content validation.
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- Skip-load-on-hit, cache eviction, and cross-node sharing remain follow-up
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work in
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[RFC #6195](https://github.com/vllm-project/vllm-omni/issues/6195).
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See the [Cosmos3 DistOffload recipe](https://github.com/vllm-project/vllm-omni/blob/main/recipes/cosmos3/Cosmos3-DistOffload.md)
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