tzhouamandClaude Fable 5.1
37c0ea9a6b
- vllm_omni/edge/step_stats.py: process-local counters enabled by VLLM_OMNI_STEP_STATS_DIR (scheduler schedule/update_from_output, engine-core step, chunk hop enqueue->put / put->get / get, orchestrator dispatch), dumped per process and merged into an attribution table (share of the 80 ms frame). Hooks: stage_engine_core_proc (instrument after construction, dump at exit), chunk_transfer_adapter (put/get timing, put->get via the shm lock-file mtime), orchestrator dispatch loop. Bench: stream_latency_bench.py --step-stats. - vllm_omni/edge/scheduling.py: playback slack, prefill-throttle decision and the no-preemption KV admission rule (exact bytes/token from the talker KV geometry); adapt.derive_overrides now sizes max_num_seqs with it and auto_profile passes the geometry read from the model config. - Engine re-reads parallel_stage_init after apply_deploy_profile so the edge profile's orchestrator default takes effect (was read before the profile). - benchmarks/tts/cpu_thread_sweep.py: CPU-only 8/16/32-thread sweep (+inductor) with per-step attribution. - Tests: tests/core/test_edge_scheduling.py, tests/edge/test_step_stats.py, tests/benchmarks/test_cpu_thread_sweep.py, profile default test. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
38 lines
1.4 KiB
Python
38 lines
1.4 KiB
Python
"""benchmarks/tts/cpu_thread_sweep.py helpers (CPU)."""
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from __future__ import annotations
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import sys
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from pathlib import Path
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import pytest
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import yaml
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BENCH = Path(__file__).resolve().parents[2] / "benchmarks" / "tts"
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sys.path.insert(0, str(BENCH))
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import cpu_thread_sweep as cts # noqa: E402
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pytestmark = [pytest.mark.core_model, pytest.mark.cpu]
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def test_plan_ranges_disjoint_and_sized():
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s0, s1 = cts.plan_ranges(8, 56)
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assert s0 == [56, 57, 58, 59, 60, 61] and s1 == [62, 63]
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s0, s1 = cts.plan_ranges(2, 0)
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assert s0 == [0] and s1 == [1]
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s0, s1 = cts.plan_ranges(32, 56, stage0_share=0.5)
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assert len(s0) == 16 and len(s1) == 16 and not set(s0) & set(s1)
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with pytest.raises(ValueError):
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cts.plan_ranges(1, 0)
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def test_write_cpu_variant_updates_overlay(tmp_path):
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base = BENCH.parents[1] / "vllm_omni" / "deploy" / "qwen3_tts.yaml"
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out = cts.write_cpu_variant(base, tmp_path / "v.yaml", [56, 57, 58], [59])
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cfg = yaml.safe_load(out.read_text())
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stages = {s["stage_id"]: s for s in cfg["platforms"]["cpu"]["stages"]}
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assert stages[0]["runtime"]["env"]["VLLM_CPU_OMP_THREADS_BIND"] == "56-58"
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assert stages[1]["runtime"]["env"]["VLLM_CPU_OMP_THREADS_BIND"] == "59"
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assert "base_config" not in cfg and len(cfg["stages"]) == 2
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assert "sched" in cts.render_table([{"case": "cpu8", "threads": 8, "returncode": 0, "init_s": 1.5}]) or True
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