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vllm-omni
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e5c0afc99432dba767dcb66f28b0fb9aa43ab1af
vllm-omni
/
vllm_omni
/
core
T
History
Sy03
a9e2117f5e
[Core][Model] Enable Qwen3-TTS MRV2 and optimize the TTS pipeline (
#7781
)
...
Signed-off-by: Sy03 <
1370724210@qq.com
>
2026-09-20 23:03:08 -07:00
..
prefix_cache
[Core] Refactor omni prefix cache into Manager/Controller (
#6654
)
2026-09-19 21:23:59 +08:00
sched
[Core][Model] Enable Qwen3-TTS MRV2 and optimize the TTS pipeline (
#7781
)
2026-09-20 23:03:08 -07:00
__init__.py
Initial vLLM-omni repository structure
2025-09-11 14:32:51 +08:00