Sy03andHongsheng Liu efbe4116ff [Feature] : Support disaggregated inference pipeline for Qwen3_TTS (#1161) ...

Signed-off-by: Sy03 <1370724210@qq.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>

2026-02-21 07:36:44 +08:00

..

__init__.py

Initial vLLM-omni repository structure

2025-09-11 14:32:51 +08:00

base.py

[Debug] Add trigger to concurrent stage init (#1274)

2026-02-11 14:18:18 +08:00

gpu_ar_model_runner.py

[Rebase] Rebase to vllm v0.16.0 (#1357)

2026-02-13 18:05:07 +08:00

gpu_ar_worker.py

[Rebase] Rebase to vllm v0.16.0 (#1357)

2026-02-13 18:05:07 +08:00

gpu_generation_model_runner.py

[Feature] : Support disaggregated inference pipeline for Qwen3_TTS (#1161)

2026-02-21 07:36:44 +08:00

gpu_generation_worker.py

[Rebase] Rebase to vllm v0.16.0 (#1357)

2026-02-13 18:05:07 +08:00

gpu_memory_utils.py

Process-Scoped GPU Memory Accounting (#1204)

2026-02-08 22:43:02 +08:00

gpu_model_runner.py

[Feature] : Support disaggregated inference pipeline for Qwen3_TTS (#1161)

2026-02-21 07:36:44 +08:00

mixins.py

[Hardware] Support platforms and plugin system (#774)

2026-01-28 22:12:52 +08:00