Zheng Wengangandamy-why-3459 94b1546ce3 [Model] Qwen3-Omni: register thinker-only pipeline for Instruct serve (#6284) ...

Signed-off-by: ZhengWG <zwg0606@gmail.com>
Signed-off-by: Zheng Wengang <zwg0606@gmail.com>
Co-authored-by: amy-why-3459 <wuhaiyan17@huawei.com>

2026-08-27 08:21:03 +00:00

..

composable_parallel

[Core] Composable parallel: Phase 1 strategy overlay (TP/DP/stage-replica) (RFC #4084) (#4281)

2026-07-10 21:29:24 -06:00

__init__.py

[Bugfix][NPU] Break the pytest DiffusionOutput circular import (#6293)

2026-08-18 10:11:10 +08:00

config_factory.py

Revert "[Bugfix] Restore name-based model detection for HF cache snapshot paths" (#6642)

2026-08-26 15:02:47 +08:00

endpoint_policy.py

[Rebase] Rebase to vllm 0.28.0 (#6606)

2026-08-27 06:12:55 +00:00

environment_variable_inventory.py

[Perf][Engine] Event-driven orchestration loop (opt-in) — S1 of #4855 (#5221)

2026-08-26 22:15:25 +08:00

lora.py

[Feature] Diffusion LoRA Adapter Support (PEFT compatible) for vLLM alignment (#758)

2026-01-27 10:22:40 +08:00

model.py

[Refactor][2/N Scheduler]Replace _FULL_PAYLOAD_INPUT_STAGES with a resolved stage transport capability. (#6149)

2026-08-25 15:24:59 +08:00

omni_config.py

[Diffusion] Register HWR mmap for direct DLO H2D (#6591)

2026-08-25 23:30:11 +08:00

pipeline_registry.py

[Model] Qwen3-Omni: register thinker-only pipeline for Instruct serve (#6284)

2026-08-27 08:21:03 +00:00

server_settings.py

[Frontend] Configurable video storage backends with TTL (#2531)

2026-06-19 17:41:22 -06:00

stage_config.py

[Diffusion] Register HWR mmap for direct DLO H2D (#6591)

2026-08-25 23:30:11 +08:00

yaml_util.py

[Config Refactor][1/2] Model Pipeline Configuration System (#1115)

2026-03-12 21:09:34 +08:00