Ayush Agarwal dc8a9e2f17 [Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (#2749) ...

Signed-off-by: ayushag <ayushag@nvidia.com>

2026-04-20 21:21:43 +08:00

..

__init__.py

[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (#2749)

2026-04-20 21:21:43 +08:00

pipeline_wan2_2_i2v.py

[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (#2749)

2026-04-20 21:21:43 +08:00

pipeline_wan2_2_ti2v.py

[Revert] drop Wan2.2 prompt-length enforcement from #2847 (#2877)

2026-04-20 19:19:38 +08:00

pipeline_wan2_2_vace.py

[Revert] drop Wan2.2 prompt-length enforcement from #2847 (#2877)

2026-04-20 19:19:38 +08:00

pipeline_wan2_2.py

[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (#2749)

2026-04-20 21:21:43 +08:00

scheduling_wan_euler.py

[Model] Adapt Wan2.2-I2V-A14B via LightX2V offline conversion path (#2134)

2026-04-13 14:20:04 +08:00

wan2_2_transformer.py

[PERF] Wan2.2 support rmsnorm fused op (#2583)

2026-04-16 03:21:34 -07:00

wan2_2_vace_transformer.py

[PERF] Wan2.2 support adalayernorm fused op (#2585)

2026-04-15 14:02:41 +08:00