Daniel HuangandHongsheng Liu c483a23deb [CI Patch] Qwen 2.5 CI Fixes for Intel XPU (#3083) ...

Signed-off-by: Daniel Huang <daniel1.huang@intel.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>

2026-05-07 08:08:25 +08:00

..

__init__.py

[Config Refactor][2/N] Pipeline + Deploy Config Schema (#2383)

2026-04-19 14:36:00 +12:00

lora.py

[Feature] Diffusion LoRA Adapter Support (PEFT compatible) for vLLM alignment (#758)

2026-01-27 10:22:40 +08:00

model.py

[BugFix]: recalculate model_config to fix FA3 scheduler_metadata shape mismatches (#3110)

2026-04-28 17:38:30 +08:00

pipeline_registry.py

[Config Refactor] Migrate Ming and Ming-TTS deploy/pipline configs (#3154)

2026-05-03 14:43:49 +12:00

stage_config.py

[CI Patch] Qwen 2.5 CI Fixes for Intel XPU (#3083)

2026-05-07 08:08:25 +08:00

yaml_util.py

[Config Refactor][1/2] Model Pipeline Configuration System (#1115)

2026-03-12 21:09:34 +08:00