andyluo7andHongsheng Liu 477083a103 [CI][ROCm] Fix deterministic AMD L3 blockers (#6884) ...

Signed-off-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>

2026-09-01 22:53:00 +08:00

..

amd

[CI][ROCm] Fix deterministic AMD L3 blockers (#6884)

2026-09-01 22:53:00 +08:00

common

[CI/Build] Move L1/E2E coverage to weekly and split scheduled L4/L5 pipelines (#6311)

2026-08-23 11:49:37 +08:00

cuda

[Test] Add MiniMax-H3 DLO DP2 variants and Turbo LoRA L3 test (#6556)

2026-09-01 10:48:52 +00:00

intel

[CI][XPU]switch to use vLLM base docker for XPU (#6727)

2026-08-29 09:03:00 +08:00

npu

Perf/minimax h3 dit swiglu rope cache npu (#6410)

2026-08-29 09:14:52 +00:00

release

[CI/Build] Add nightly DockerHub publish and cleanup to release pipeline (#6048)

2026-08-12 17:30:55 +08:00