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vllm-omni
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9ceca4ec85c21d1806ea69d74002e0f9e96bbca7
vllm-omni
/
vllm_omni
/
model_executor
/
models
/
common
/
ming
T
History
LHXuuu
991fb7408b
[BugFix][Ming-TTS] Improve Seed-TTS WER accuracy (
#4859
)
...
Signed-off-by: LHXuuu <
xulianhao.xlh@antgroup.com
>
2026-07-03 12:15:03 +02:00
..
__init__.py
[Model] Add Ming-omni-tts dense 0.5B pipeline (
#2906
)
2026-06-10 20:11:04 +08:00
audio_dsp.py
[Model] Add Ming-omni-tts dense 0.5B pipeline (
#2906
)
2026-06-10 20:11:04 +08:00
audio_vae.py
[BugFix][Ming-TTS] Improve Seed-TTS WER accuracy (
#4859
)
2026-07-03 12:15:03 +02:00
dit.py
[Model] Add Ming-omni-tts dense 0.5B pipeline (
#2906
)
2026-06-10 20:11:04 +08:00
fm.py
[Model] Add Ming-omni-tts dense 0.5B pipeline (
#2906
)
2026-06-10 20:11:04 +08:00
