* vllm_omni/engine/init_timeline.py: InitTimeline phase collector; engine phases (stages_init, g3_device_lock, g2_spawn/ready) and worker phases (proc_entry, engine_core_init, init_device, load_model/load_weights, talker_mtp_init, attn_prewarm, cudagraph_capture, talker_mtp_capture, code2wav_cudagraph, predictor_setup_compile/warmup/cudagraph) recorded via worker_phase/timed_phase; workers append JSONL under VLLM_OMNI_INIT_TIMELINE_DIR (inherited at spawn) and the engine merges them. Enabled by VLLM_OMNI_INIT_TIMELINE=<json> or log_stats; table logged at INFO, partial table on orchestrator startup timeout, suggested timeouts logged. * omni_base.py: named deploy profiles default to stage_init_timeout=900 / init_timeout=1500 unless given explicitly. * gpu_model_runner._init_talker_mtp tolerates max_cudagraph_capture_size=None; gpu_ar_model_runner.shutdown skips CUDA graph teardown on CPU. * benchmarks/tts/init_profile.py: runs stream_latency_bench --init-only per configuration (default, cold_cache, eager_stage1, eager_both, parallel_stage_init, edge, ...) and tabulates phase durations. * stream_latency_bench: --parallel-stage-init / --deploy-profile flags; the resource poller no longer shadows Thread._stop and skips GPU sampling on CPU. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
61 lines
2.3 KiB
Python
61 lines
2.3 KiB
Python
"""Tests for benchmarks/tts/init_profile.py helpers (CPU)."""
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from __future__ import annotations
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import sys
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from pathlib import Path
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import pytest
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import yaml
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sys.path.insert(0, str(Path(__file__).parent.parent.parent / "benchmarks" / "tts"))
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import init_profile as ip # noqa: E402
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pytestmark = [pytest.mark.core_model, pytest.mark.cpu]
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def test_flatten_edge_yaml_inherits_base_and_applies_updates(tmp_path):
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edge = ip.DEPLOY_DIR / "edge" / "qwen3_tts.yaml"
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flat = ip._flatten_deploy_yaml(edge)
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assert "base_config" not in flat
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assert [s["stage_id"] for s in flat["stages"]] == [0, 1]
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# inherited from base
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assert flat["stages"][0]["trust_remote_code"] is True
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# overridden by edge
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assert flat["stages"][0]["max_num_seqs"] == 4
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assert flat["connectors"]["connector_of_shared_memory"]["extra"]["codec_chunk_ramp"] == [2, 4, 8, 16, 25]
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out = ip.write_variant_yaml(
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edge, {"stages": {1: {"enforce_eager": True}}, "top": {"async_chunk": False}}, tmp_path, "v"
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)
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doc = yaml.safe_load(out.read_text())
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assert doc["stages"][1]["enforce_eager"] is True
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assert doc["stages"][0].get("enforce_eager") is None
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assert doc["async_chunk"] is False
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def test_phase_durations_and_table():
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timeline = {
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"total_s": 100.0,
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"phases": [
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{"name": "load_weights", "dur_s": 10.0, "stage_id": 0},
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{"name": "load_weights", "dur_s": 5.0, "stage_id": 1},
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{"name": "predictor_setup_compile", "dur_s": 40.0, "stage_id": 0},
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],
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}
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d = ip.phase_durations(timeline)
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assert d == {"load_weights": 15.0, "predictor_setup_compile": 40.0}
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by_stage = ip.phase_durations_by_stage(timeline)
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assert by_stage["0"]["load_weights"] == 10.0 and by_stage["1"]["load_weights"] == 5.0
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table = ip.render_table([{"config": "default", "init_s": 100.0, "ttfa_ms": 30.0, "gpu_mib": 5000, "phases": d}])
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assert "| default | 100.0 | 30.0 | 5000 |" in table
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assert "predictor_setup_compile" in table.splitlines()[0]
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assert ip.phase_durations(None) == {}
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def test_config_registry_names():
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for name in ("default", "cold_cache", "eager_stage1", "eager_both", "parallel_stage_init", "edge"):
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assert name in ip.CONFIGS
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assert ip.CONFIGS["cold_cache"].fresh_caches is True
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assert ip.CONFIGS["parallel_stage_init"].extra_args == ["--parallel-stage-init"]
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