This website requires JavaScript.
Explore
Help
Sign In
anodyine
/
vllm-omni
Watch
1
Star
0
Fork
0
Code
Issues
4
Pull Requests
2
Actions
Packages
Projects
Releases
Wiki
Activity
Files
687a44e5c83cedf16882b188ce0b042197fe69c8
vllm-omni
/
tests
/
diffusion
/
models
/
dmd2
T
History
Ayush Agarwal
dc8a9e2f17
[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (
#2749
)
...
Signed-off-by: ayushag <
ayushag@nvidia.com
>
2026-04-20 21:21:43 +08:00
..
__init__.py
[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (
#2749
)
2026-04-20 21:21:43 +08:00
test_dmd2_request_sanitization.py
[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (
#2749
)
2026-04-20 21:21:43 +08:00
test_dmd2_scheduler.py
[Model] feat: FastGen DMD2-distilled Wan 2.1 pipelines (T2V, I2V) (
#2749
)
2026-04-20 21:21:43 +08:00
