Chenchao Xu d0755b5716 [Model] Add π0.5 (Pi0.5) VLA model support (#6950) ...

Signed-off-by: chenchaox <chenchaox@nvidia.com>

2026-09-17 05:18:51 -07:00

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amd

[CI][ROCm] Add non-blocking entrypoint GPU coverage (#7398)

2026-09-16 07:25:56 +08:00

common

[Core] Give the OpenAI Realtime wire codec a reusable home (RFC #6592 P0a) (#7640)

2026-09-17 02:33:40 -07:00

cuda

[Model] Add π0.5 (Pi0.5) VLA model support (#6950)

2026-09-17 05:18:51 -07:00

intel

[XPU][Docker] Align XPU image and CI with vLLM v0.29.0 (#7441)

2026-09-11 15:54:28 -05:00

npu

[CI/Build] Diff-aware source_file_dependencies for CUDA/NPU pipelines (#6597)

2026-09-10 01:40:01 -07:00

release

[CI/Build] Add nightly DockerHub publish and cleanup to release pipeline (#6048)

2026-08-12 17:30:55 +08:00