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anodyine/vllm-omni
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Code Issues 4 Pull Requests 2 Actions Packages Projects Releases Wiki Activity
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44cde33eb5b08b09e1d7a42d320b9ef5aa87f830
vllm-omni/docs/design/feature/omni_connectors
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Jinhengahengljhnatureofnature
c3c736d488 [Feature] Port Bagel RDMA flow to latest main (#2000)
Signed-off-by: Jinheng Li <ahengljh@gmail.com>
Signed-off-by: natureofnature <wzliu@connect.hku.hk>
Co-authored-by: ahengljh <ahengljh@users.noreply.github.com>
Co-authored-by: natureofnature <wzliu@connect.hku.hk>
2026-04-08 14:55:35 +08:00
..
mooncake_store_connector.md
[skip CI][Docs] add connector design document (#1737)
2026-03-13 09:23:32 +08:00
mooncake_transfer_engine_connector.md
[Feature] Port Bagel RDMA flow to latest main (#2000)
2026-04-08 14:55:35 +08:00
shared_memory_connector.md
[skip CI][Docs] add connector design document (#1737)
2026-03-13 09:23:32 +08:00
yuanrong_connector.md
[skip CI][Docs] add connector design document (#1737)
2026-03-13 09:23:32 +08:00
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