Yichen WangandDidan Deng 2a9f6aaa8e Add π0 VLA model support (#4222) ...

Signed-off-by: Yichen Wang <yichen.wang@bytedance.com>
Signed-off-by: Didan Deng <33117903+wtomin@users.noreply.github.com>
Co-authored-by: Didan Deng <33117903+wtomin@users.noreply.github.com>

2026-08-17 14:29:17 +08:00

..

accuracy

[CI]demote slow nightly cases and trim Qwen-Image-Edit coverage (#5944)

2026-08-17 11:21:28 +08:00

features

[Refactor][OutputProcessor 2/8]: OmniRequestOutput should inherit RequestOutput and no nested wrap-up (#5146)

2026-08-12 22:58:23 +08:00

offline_inference

[CI]demote slow nightly cases and trim Qwen-Image-Edit coverage (#5944)

2026-08-17 11:21:28 +08:00

online_serving

Add π0 VLA model support (#4222)

2026-08-17 14:29:17 +08:00

__init__.py

[ROCm] [CI] Add ROCm Dockerfile and AMD CI (vllm v0.12.0) (#280)

2025-12-21 11:51:37 +08:00