dsinghviandZhou Taichang 68764cc4f4 [Refactor]: Phase1 for rebasing_additional_info (#1394) ...

Signed-off-by: dsinghvi <divyanshsinghvi@gmail.com>
Signed-off-by: Divyansh Singhvi <divyanshsinghvi@gmail.com>
Signed-off-by: Zhou Taichang <tzhouam@connect.ust.hk>
Co-authored-by: Zhou Taichang <tzhouam@connect.ust.hk>

2026-03-02 10:19:41 +08:00

..

__init__.py

Initial vLLM-omni repository structure

2025-09-11 14:32:51 +08:00

base.py

[Debug] Add trigger to concurrent stage init (#1274)

2026-02-11 14:18:18 +08:00

gpu_ar_model_runner.py

[Refactor]: Phase1 for rebasing_additional_info (#1394)

2026-03-02 10:19:41 +08:00

gpu_ar_worker.py

[Rebase] Rebase to vllm v0.16.0 (#1357)

2026-02-13 18:05:07 +08:00

gpu_generation_model_runner.py

[Performance]Qwen3-Omni performance optimization (#1378)

2026-02-26 21:21:36 +08:00

gpu_generation_worker.py

[Rebase] Rebase to vllm v0.16.0 (#1357)

2026-02-13 18:05:07 +08:00

gpu_memory_utils.py

Process-Scoped GPU Memory Accounting (#1204)

2026-02-08 22:43:02 +08:00

gpu_model_runner.py

[Refactor]: Phase1 for rebasing_additional_info (#1394)

2026-03-02 10:19:41 +08:00

mixins.py

[Hardware] Support platforms and plugin system (#774)

2026-01-28 22:12:52 +08:00