Yuan WuandHongsheng Liu
cb5f508212
Signed-off-by: yuanwu <yuan.wu@intel.com> Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
50 lines
1.2 KiB
YAML
50 lines
1.2 KiB
YAML
# MiniMax H3 Turbo: five-sigma defaults for the disaggregated topology.
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pipeline: minimax_h3_disaggregated
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async_chunk: false
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trust_remote_code: true
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distributed_executor_backend: mp
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connectors:
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shared_memory_connector:
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name: SharedMemoryConnector
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stages:
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- stage_id: 0
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devices: "0,1"
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max_num_seqs: 1
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gpu_memory_utilization: 0.6
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tensor_parallel_size: 2
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output_connectors:
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to_stage_1: shared_memory_connector
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hf_overrides:
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minimax_h3_encoder_components:
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text_encoder:
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parallel_mode: tp
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video_vae:
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parallel_mode: patch
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audio_vae:
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parallel_mode: leader
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default_sampling_params:
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max_tokens: 1
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temperature: 0.0
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detokenize: false
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- stage_id: 1
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devices: "2,3,4,5"
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max_num_seqs: 1
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model_loaded:
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text_encoder: false
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vae_encoder: false
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parallel_config:
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tensor_parallel_size: 1
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ulysses_degree: 4
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vae_patch_parallel_size: 4
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input_connectors:
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from_stage_0: shared_memory_connector
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default_sampling_params:
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seed: 42
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num_inference_steps: 5
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extra_args:
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flow_shift: 6.0
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audio_flow_shift: 3.0
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