hsliuustc0106 b188874539 [Perf][Diffusion] Add configurable H3 VAE stacked tiling ...

Signed-off-by: hsliuustc0106 <liuhongsheng4@huawei.com>

2026-09-03 17:17:59 +00:00

..

composable_parallel

[Core] Composable parallel: Phase 1 strategy overlay (TP/DP/stage-replica) (RFC #4084) (#4281)

2026-07-10 21:29:24 -06:00

__init__.py

[Bugfix][NPU] Break the pytest DiffusionOutput circular import (#6293)

2026-08-18 10:11:10 +08:00

config_factory.py

[Feature] Support text encoder Disaggregation for H3 (#5885)

2026-08-28 14:27:05 +08:00

endpoint_policy.py

[Bugfix] Fix vLLM serve error response imports (#6707)

2026-09-02 15:48:01 -07:00

environment_variable_inventory.py

[Feature][MiniMax-H3] Complete VSA and Ulysses support (#6909)

2026-09-02 07:19:21 -04:00

lora.py

[Feature] Diffusion LoRA Adapter Support (PEFT compatible) for vLLM alignment (#758)

2026-01-27 10:22:40 +08:00

model.py

[Bugfix] Gate async-chunk segment resume by session mode (#6680)

2026-08-27 18:52:09 +08:00

omni_config.py

[Perf][Diffusion] Add configurable H3 VAE stacked tiling

2026-09-03 17:17:59 +00:00

pipeline_registry.py

[Core] Validate PipelineConfig in __post_init__ (#6829)

2026-09-01 11:17:57 +08:00

server_settings.py

[Frontend] Configurable video storage backends with TTL (#2531)

2026-06-19 17:41:22 -06:00

stage_config.py

[Perf][Diffusion] Add configurable H3 VAE stacked tiling

2026-09-03 17:17:59 +00:00

yaml_util.py

[Config Refactor][1/2] Model Pipeline Configuration System (#1115)

2026-03-12 21:09:34 +08:00