 Joshna-Medisetty
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62ebad2d7c
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Add Intel Arc BMG recipes for validated P0 diffusion models. (#7537)
Signed-off-by: Joshna-Medisetty <joshna.medisetty@intel.com>
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2026-09-25 15:42:08 -05:00 |
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wangyu
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0570b0da7e
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[CI][Perf] migrate diffusion DFX benches to vllm bench serve --omni (#7737)
Signed-off-by: wangyu <410167048@qq.com>
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2026-09-21 19:16:39 -07:00 |
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Mu GuanLin
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3204a0b2ad
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[Model][Perf] Optimize LTX Ulysses sequence parallelism (#7079)
Signed-off-by: mglyn <1203789601@qq.com>
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2026-09-07 10:48:26 +00:00 |
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SYLAR
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ce6ab0ca46
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[Model] Add LTX-2.5 support (#6070)
Signed-off-by: lishunyang12 <lishunyang12@163.com>
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2026-08-15 18:27:23 +08:00 |
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Mu GuanLin
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83d1f11449
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[Feat] LTX Standard Two-Stage Pipeline (#5500)
Signed-off-by: mglyn <1203789601@qq.com>
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2026-08-14 00:13:14 +08:00 |
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bjf-frz
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9f978923f2
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[docs] consolidate diffusion execution modes (#5599)
Signed-off-by: bjf-frz <frz123db@gmail.com>
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2026-08-05 22:41:18 +08:00 |
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Mu GuanLin
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1b718f7b15
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[Feat] [CI] [bugfix] Generalize LTX CFG parallelism to the complete guidance plan (#5547)
Signed-off-by: mglyn <1203789601@qq.com>
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2026-07-29 17:40:40 +00:00 |
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Mu GuanLin
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12d75cf63a
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[Feature] Add official LTX multimodal guidance and precision guard (#5148)
Signed-off-by: mglyn <1203789601@qq.com>
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2026-07-28 10:44:25 +00:00 |
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Hongsheng Liuanddeepseek-v4-pro
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c0e132d973
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[Doc] Reorganize available recipes into a table (#3671)
Signed-off-by: hsliu <liuhongsheng4@huawei.com>
Co-authored-by: deepseek-v4-pro <noreply@anthropic.com>
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2026-05-18 00:02:34 +08:00 |
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fywc
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e969d2e99f
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[Docs] Add LTX-2-T2V and LTX-2-I2V recipes (#3294)
Signed-off-by: hanzheli <hanzheli@kuaishou.com>
Signed-off-by: fywc <hanzheli@kuaishou.com>
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2026-05-06 03:11:22 -07:00 |
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