WeiQing Chen
|
84977d9543
|
[Bugfix][MiniMax-H3] Fix Hopper keyframe and modulation precision (#7913)
Signed-off-by: david6666666 <530634352@qq.com>
|
2026-09-21 16:26:09 +08:00 |
|
汪志鹏
|
139a47a578
|
[Model] Add MiniMax-H3 long-video latent continuation with driving audio (#7838)
Signed-off-by: princepride <wangzhipeng628@gmail.com>
|
2026-09-20 23:44:33 +08:00 |
|
xiaoyu-xyz
|
5a93ec1b4e
|
[Model][Frontend] MiniMax-H3: Add latent-mask editing (#7465)
Signed-off-by: xiaoyu <1259084489@qq.com>
|
2026-09-20 03:54:44 +00:00 |
|
ooooooye
|
a9abd563f9
|
[Bugfix][RAINFUSION_ATTN] Fix padding-mask rejection on packed [real, pad] layouts and reuse query tail as output padding (#7235)
Signed-off-by: brandneway <gyuan4892@gmail.com>
|
2026-09-20 10:56:51 +08:00 |
|
Anjie Hou
|
f8197e120f
|
[5/N] Schedule chunk transfers as their own stage (#7406)
Signed-off-by: specture724 <specture724@gmail.com>
|
2026-09-18 09:27:56 +08:00 |
|
 
|
2ab5d1701a
|
[4/N] Unify worker-side MP4 encoding and wire Wan into it (#7048)
Signed-off-by: specture724 <specture724@gmail.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
|
2026-09-17 23:33:56 +08:00 |
|
WeiQing Chen
|
cb439f3e84
|
[Diffusion][Model] Add direct FastH3 8-Step V2 checkpoint loading (#7610)
Signed-off-by: david6666666 <530634352@qq.com>
|
2026-09-17 08:41:52 +00:00 |
|
 
|
d554e6b67e
|
[feat] Extend disaggregated MiniMax-H3 stage with VAE encoders (#6939)
Signed-off-by: asukaqaq-s <1311722138@qq.com>
Signed-off-by: Jader <yjader@foxmail.com>
Co-authored-by: Jader <yjader@foxmail.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
|
2026-09-16 16:52:35 +08:00 |
|
heyuanliu-intel
|
40f8e94400
|
[Model][MiniMax-H3] Multi-GPU serving fixes and layer-wise offload component selection (#7047)
Signed-off-by: heyuanliu-intel <heyuan.liu@intel.com>
|
2026-09-14 10:02:30 -07:00 |
|
 
|
7e520f9cc4
|
[3/N] Encode streamed video on the worker with bounded batching (#7018)
Signed-off-by: specture724 <specture724@gmail.com>
Co-authored-by: Claude Sonnet 5 <noreply@anthropic.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
|
2026-09-12 20:58:11 +08:00 |
|
WeiQing Chen
|
3d952d1334
|
[Bugfix] Keep MiniMax-H3 reference audio budgets separate (#7281)
Signed-off-by: david6666666 <530634352@qq.com>
|
2026-09-11 09:26:35 +08:00 |
|
Chenguang Zheng
|
087ac46318
|
[Refactor 1/N] Centralize Omni config resolution (#5140)
Signed-off-by: Chenguang ZHENG <645327136@qq.com>
|
2026-09-08 10:30:26 +08:00 |
|
WeiQing Chen
|
30d6a0b4e6
|
[Bugfix][MiniMax-H3] Stabilize keyframe VAE encoding (#7191)
Signed-off-by: david6666666 <530634352@qq.com>
Signed-off-by: David Chen <530634352@qq.com>
|
2026-09-07 21:52:54 +08:00 |
|
Hongsheng Liu
|
715b8b8746
|
[Model] MiniMax-H3: validate versioned text-conditioning handoff (#6720)
Signed-off-by: hsliuustc0106 <liuhongsheng4@huawei.com>
|
2026-09-06 21:45:10 +08:00 |
|
 汪志鹏andClaude Opus 5
|
af74a5a155
|
[Feature][MiniMax-H3] Support the full LightX2V Turbo LoRA matrix (#7062)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
|
2026-09-06 20:23:36 +08:00 |
|
SYLAR
|
ea3cf99894
|
[diffusion][feature] Add component-selective offload policies (#5929)
Signed-off-by: lishunyang12 <lishunyang12@163.com>
|
2026-09-06 05:40:09 +08:00 |
|
汪志鹏
|
c59b48b47e
|
[Feature][MiniMax-H3] Complete VSA and Ulysses support (#6909)
Signed-off-by: princepride <wangzhipeng628@gmail.com>
Signed-off-by: 汪志鹏 <wangzhipeng628@gmail.com>
|
2026-09-02 07:19:21 -04:00 |
|
 汪志鹏andHongsheng Liu
|
86b85c078b
|
[Feature][MiniMax-H3] Fuse the FastH3 four-step adapter at load time (#6714)
Signed-off-by: princepride <wangzhipeng628@gmail.com>
Signed-off-by: Hongsheng Liu <liuhongsheng4@huawei.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
|
2026-08-31 12:04:58 +08:00 |
|
SYLAR
|
759aa4ffeb
|
[Diffusion][Performance] Optimize MiniMax-H3 video output transfer (#6824)
Signed-off-by: lishunyang12 <lishunyang12@163.com>
|
2026-08-31 07:07:34 +08:00 |
|
 
|
b6a4baa659
|
[Feature] Support text encoder Disaggregation for H3 (#5885)
Signed-off-by: Canlin Guo <canlinguosdu@gmail.com>
Signed-off-by: lishunyang12 <lishunyang12@163.com>
Signed-off-by: yuanwu <yuan.wu@intel.com>
Co-authored-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: yuanwu <yuan.wu@intel.com>
|
2026-08-28 14:27:05 +08:00 |
|
XiongZhongwei
|
40dcfdbb43
|
[Perf][NPU] Enable native GQA & fused AddNorm for MiniMax-H3 encoder (#6040)
Signed-off-by: MarkPoloChina <1228479724@qq.com>
Signed-off-by: XiongZhongwei <1228479724@qq.com>
|
2026-08-26 09:14:05 +08:00 |
|
Bo Li
|
51b7565f33
|
[perf] Add mask-free TRTLLM packed-padding path (#6542)
Signed-off-by: Bo Li <22713281+bobboli@users.noreply.github.com>
|
2026-08-25 07:45:21 +00:00 |
|
  
|
d150a4fde7
|
[Feature][MiniMax-H3] Support diffusion continuous batching (#5810)
Signed-off-by: princepride <wangzhipeng628@gmail.com>
Signed-off-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-08-24 21:08:53 +08:00 |
|
 Mu GuanLinandHongsheng Liu
|
3d035bfa19
|
[Feature] Support MiniMax-H3 Turbo LoRA with the legacy manager (#6476)
Signed-off-by: mglyn <1203789601@qq.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
|
2026-08-24 06:21:42 +08:00 |
|
R0CKSTAR
|
260db8bab5
|
[Bugfix][Diffusion] Fix MiniMax-H3 model-level CPU offload residency (#6072)
Signed-off-by: Xiaodong Ye <xiaodong.ye@mthreads.com>
|
2026-08-21 10:30:53 +00:00 |
|
 SYLARandHongsheng Liu
|
d1e230c95b
|
[Diffusion][Quantization] Enable MiniMax-H3 global FP8 with DLO (#5910)
Signed-off-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
|
2026-08-15 23:01:26 +08:00 |
|
R0CKSTAR
|
022d7a7695
|
[Perf][Diffusion] Avoid redundant MiniMax-H3 reference video scans (#6064)
Signed-off-by: Xiaodong Ye <xiaodong.ye@mthreads.com>
|
2026-08-14 15:49:26 +08:00 |
|
 Zijun HuangandWeiQing Chen
|
1a56953d7a
|
[NPU][Model] Add distilled 4-step sigma schedule support for MiniMax H3 t2va (#5991)
Signed-off-by: Zijun Huang <zijunhua@usc.edu>
Co-authored-by: WeiQing Chen <40507679+david6666666@users.noreply.github.com>
|
2026-08-11 13:46:10 +08:00 |
|
WeiQing Chen
|
1f65814fab
|
[CI] Align MiniMax H3 Ref2VA inputs and add I2VA/Ref2VA accuracy coverage (#5978)
Signed-off-by: david6666666 <530634352@qq.com>
|
2026-08-11 13:36:37 +08:00 |
|
ooooooye
|
740f45abcd
|
[Perf][Diffusion] MiniMax-H3: opt into packed varlen attention on NPU to eliminate quadratic mask materialization (#5891)
Signed-off-by: brandneway <gyuan4892@gmail.com>
|
2026-08-10 19:47:03 +08:00 |
|
 Shenglei FuandClaude Opus 5
|
81b48e83ec
|
[Model] Fail MiniMax H3 encoder load when a weight or fused shard is missing (#5824)
Signed-off-by: Shenglei Fu <sfu@confluent.io>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-08-08 13:14:00 +08:00 |
|
Mu GuanLin
|
d8c35663b4
|
[Model][Feat] Support Minimax-H3 quality grading requests through dynamic loading/unloading with Cache-DiT (#5853)
Signed-off-by: mglyn <1203789601@qq.com>
|
2026-08-07 09:07:23 +00:00 |
|
  
|
48298030d4
|
[Diffusion] Add Minimax-H3 modular pipeline support (#5720)
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
Signed-off-by: lishunyang12 <lishunyang12@163.com>
Signed-off-by: David Chen <530634352@qq.com>
Co-authored-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: SYLAR <125541396+lishunyang12@users.noreply.github.com>
Co-authored-by: David Chen <530634352@qq.com>
|
2026-08-06 11:43:23 +00:00 |
|
 SYLARandlishunyang12
|
1c2a81f6d8
|
feat(minimax-h3): enable 2x RTX 4090/5090 with DLO (#5764)
Signed-off-by: lishunyang12 <lishunyang03@gmail.com>
Signed-off-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: lishunyang12 <lishunyang03@gmail.com>
|
2026-08-06 09:02:29 +08:00 |
|
WeiQing Chen
|
ae7bee0c43
|
[Feature] Align MiniMax H3 official input matrix (#5752)
Signed-off-by: david6666666 <530634352@qq.com>
|
2026-08-05 07:12:01 +00:00 |
|
Isotr0py
|
24741961eb
|
[Model] Add MiniMax H3 diffusion support (#5691)
|
2026-08-03 14:10:40 +08:00 |
|