anodyine/vllm-omni
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2 Commits
Author SHA1 Message Date
andyluo7 de1b0708bd [CI][ROCm] Route LTX2 Ulysses parity to two-GPU lane (#7234) 
Signed-off-by: andyluo7 <andy.luo@amd.com>
 2026-09-08 22:59:37 +08:00
Mu GuanLin 3204a0b2ad [Model][Perf] Optimize LTX Ulysses sequence parallelism (#7079) 
Signed-off-by: mglyn <1203789601@qq.com>
 2026-09-07 10:48:26 +00:00