 Juan Pablo Zuluagaandpablo
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1d0a97f0d1
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[feat][Qwen3TTS] Simple dynamic TTFA based on Code2Wav load (#1714)
Signed-off-by: pablo <pablo@agigo.ai>
Co-authored-by: pablo <pablo@agigo.ai>
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2026-03-10 21:02:33 +00:00 |
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Juan Pablo Zuluagaandpablo
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6a45efb287
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[Feat][Qwen3TTS] reduce TTFA with flexible initial phase (#1583)
Signed-off-by: pablo <pablo@agigo.ai>
Co-authored-by: pablo <pablo@agigo.ai>
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2026-03-05 23:14:41 +08:00 |
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dsinghviandZhou Taichang
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68764cc4f4
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[Refactor]: Phase1 for rebasing_additional_info (#1394)
Signed-off-by: dsinghvi <divyanshsinghvi@gmail.com>
Signed-off-by: Divyansh Singhvi <divyanshsinghvi@gmail.com>
Signed-off-by: Zhou Taichang <tzhouam@connect.ust.hk>
Co-authored-by: Zhou Taichang <tzhouam@connect.ust.hk>
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2026-03-02 10:19:41 +08:00 |
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Canlin Guo
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c81266703a
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[NPU][Bugfix] Align GPU side and recover qwen3-tts (#1564)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
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2026-02-28 12:46:13 +08:00 |
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Chendi.Xueandgcanlin
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482f9b89a1
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[XPU][NPU][ROCM] enable cpu_offloading flag for non_cuda (#1488)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Co-authored-by: gcanlin <canlinguosdu@gmail.com>
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2026-02-27 14:52:15 +08:00 |
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Chendi.XueandHongsheng Liu
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43a9e48ff7
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[XPU] fix qwen_omni after rebase to v0.16.0 (#1416)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-02-27 06:44:48 +08:00 |
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Canlin Guo
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22c8cde328
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[NPU] Upgrade to v0.16.0 (#1375)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
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2026-02-26 14:26:50 +08:00 |
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Yanick Schraner
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97f4c5b1e7
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[Bugfix] Add TTS configuration options (#1177)
Signed-off-by: Yanick Schraner <yanick.schraner@bs.ch>
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2026-02-26 00:14:44 +08:00 |
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Sy03andHongsheng Liu
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efbe4116ff
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[Feature] : Support disaggregated inference pipeline for Qwen3_TTS (#1161)
Signed-off-by: Sy03 <1370724210@qq.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-02-21 07:36:44 +08:00 |
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Chendi.Xue
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d2f015edce
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[0.16.0] remove cuda hard-code for Hunyuan Image3 (#1402)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
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2026-02-20 13:23:31 +08:00 |
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amy-why-3459
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5304bc1e16
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[Refactor] Refactor async chunk and fix the shape mismatch issue (#1151)
Signed-off-by: amy-why-3459 <wuhaiyan17@huawei.com>
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2026-02-04 00:00:56 +08:00 |
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liuzhenwei
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6c19f3e386
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[Hardware] Disable compile of diffusion on XPU (#1148)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
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2026-02-03 12:28:06 +00:00 |
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Canlin Guo
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722a69e8d1
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[NPU] Align with GPUModelRunner (#1114)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
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2026-01-31 04:26:34 +00:00 |
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Canlin Guo
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4eeea68cff
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[Platform] Add supports_torch_inductor interface (#1108)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
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2026-01-30 15:21:43 +00:00 |
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Fanli LinandCopilot
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bfbf3e5b69
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[Feat] Support XPU Backend in vLLM-Omni (#191)
Signed-off-by: Fanli Lin <fanli.lin@intel.com>
Signed-off-by: Fanli Lin <fanli0116@gmail.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
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2026-01-30 04:33:05 +13:00 |
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Ziming Huang
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c48a9f33ad
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[CI] Change Qwen3 Omni stage placement strategy (#1072)
Signed-off-by: ZeldaHuang <hzm414167@alibaba-inc.com>
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2026-01-30 02:10:09 +13:00 |
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XU MingshiandHongsheng Liu
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5b8ade8446
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[Diffusion][Bugfix] Fix the flash_attn backends selection logic (#983)
Signed-off-by: mxuax <mxuax@connect.ust.hk>
Signed-off-by: XU Mingshi <91017482+mxuax@users.noreply.github.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-01-29 16:44:58 +08:00 |
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Canlin Guo
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c9392dff01
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[Hardware] Support platforms and plugin system (#774)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
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2026-01-28 22:12:52 +08:00 |
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