 Sy03
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473da2cf82
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[Perf][Qwen3-TTS] Enable event-driven orchestration by default (#7088)
Signed-off-by: Sy03 <1370724210@qq.com>
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2026-09-21 12:09:19 -07:00 |
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Sy03
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a9e2117f5e
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[Core][Model] Enable Qwen3-TTS MRV2 and optimize the TTS pipeline (#7781)
Signed-off-by: Sy03 <1370724210@qq.com>
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2026-09-20 23:03:08 -07:00 |
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Zhou TaichangandClaude Fable 5
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142151fef5
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Parallel stage initialization (admission + SH/EX device locks) (Worker refactor 1/N) (#5224)
Signed-off-by: Taichang Zhou <tzhouam@connect.ust.hk>
Signed-off-by: tzhouam <tzhouam@connect.ust.hk>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-09-05 22:22:41 +08:00 |
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bb5bf8fd0a
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[Bugfix] Fix colocate-async sleep admission race and deliver AR abort tokens (#6367)
Signed-off-by: knlnguyen1802 <knlnguyen1802@gmail.com>
Signed-off-by: Cursor <cursoragent@cursor.com>
Signed-off-by: Samit <285365963@qq.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Samit <285365963@qq.com>
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2026-08-29 09:11:39 +00:00 |
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Zhou TaichangandClaude Opus 5
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2ce15ab7a0
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[Rebase] Rebase to vllm 0.27.0 (#5976)
Signed-off-by: tzhouam <tzhouam@connect.ust.hk>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-08-11 15:23:46 +00:00 |
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Zhou TaichangandClaude Opus 4.8
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776424f0de
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[Refactor][WIP] Add missing test for modelrunner (G1/N) (#5333)
Signed-off-by: Taichang Zhou <tzhouam@connect.ust.hk>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-07-27 16:24:47 +08:00 |
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