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33297bdb9dccc8c0c63c2e95bdfa617964b88db6
Commit Graph
528 Commits
Author SHA1 Message Date
hsliuustc0106 f4394f1d3d [Model] Prime DLO cache retention with a startup warmup 
Models whose request geometry opts out of the generic dummy run (H3: t2va
needs an explicit aspect ratio and a bounded duration) can declare a
dlo_dummy_run_recipe. Under distributed layerwise offload the engine's
startup warmup runs it, so the learned cache-retention budget is primed
before real traffic instead of on the first request.

H3 declares a maximum-duration t2va generation: duration is the only
workload variable at the fixed 768 short edge, so the learned peak
dominates every production request and no real request re-learns. Validated
on L20X: all cold-start releases happen during the startup warmup, zero
during requests; first request 15.91 s vs 16.7 s unwarmed, steady 14.9 s;
startup gains one max-length generation (~10-20 s). Non-DLO deployments
keep the opted-out generic warmup unchanged.

Signed-off-by: hsliuustc0106 <liuhongsheng4@huawei.com>
 2026-08-26 15:06:08 +08:00
Hongsheng Liu 5a8b81ebeb [Model] Optimize MiniMax-H3 DLO component lifecycle (#6526) 
Signed-off-by: hsliuustc0106 <liuhongsheng4@huawei.com>
 2026-08-25 23:13:41 +08:00
Bo Li 51b7565f33 [perf] Add mask-free TRTLLM packed-padding path (#6542) 
Signed-off-by: Bo Li <22713281+bobboli@users.noreply.github.com>
 2026-08-25 07:45:21 +00:00
yzong-rh 710024fa6f [Bugfix] Honor height/width overrides in LongCatImageEditPipeline (#6222) 
Signed-off-by: Yifan Zong <yzong@redhat.com>
 2026-08-25 02:09:00 +00:00
leoandleo 50b8a150f9 [Model] Add native SANA-Video 2B T2V and I2V support (#5508) 
Signed-off-by: leo <92263211+napleon-liu@users.noreply.github.com>
Signed-off-by: leo <92263211+liuyao0322@users.noreply.github.com>
Signed-off-by: liuyao0322 <yaoliu548926@gmail.com>
Co-authored-by: leo <92263211+napleon-liu@users.noreply.github.com>
 2026-08-25 09:46:02 +08:00
汪志鹏Claude Opus 5lishunyang12Cursor
 		d150a4fde7 [Feature][MiniMax-H3] Support diffusion continuous batching (#5810) 
Signed-off-by: princepride <wangzhipeng628@gmail.com>
Signed-off-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-08-24 21:08:53 +08:00
bjf-frzandHongsheng Liu 072bfc02dd [FEAT]Add FastVideo VSA backend for Wan2.2 (#4820) 
Signed-off-by: bjf-frz <frz123db@gmail.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-24 14:48:31 +08:00
Mu GuanLinandHongsheng Liu 3d035bfa19 [Feature] Support MiniMax-H3 Turbo LoRA with the legacy manager (#6476) 
Signed-off-by: mglyn <1203789601@qq.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-24 06:21:42 +08:00
wangyu 1e2a6446f7 [CI] Remove AudioX and MammothModa2 support (#6353) 
Signed-off-by: wangyu <410167048@qq.com>
 2026-08-23 04:22:05 +00:00
wangyu 2e096788a6 [CI]Remove SoulX-Singer support (#6362) 
Signed-off-by: wangyu <410167048@qq.com>
 2026-08-23 07:16:32 +08:00
Wang fuyinandHongsheng Liu 72ee535fcd [Diffusion] Add native paged KV backend for diffusion workers (#6102) 
Signed-off-by: Acerak01-fy <wfy2003324@163.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-22 21:45:45 +08:00
Hongsheng Liu 493fc64397 [Diffusion] Add final-layout BF16 Host Weight Runtime artifacts (#6445) 
Signed-off-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-22 21:37:20 +08:00
yzong-rh 3d34b8b977 [Bugfix] Fix LongCat TeaCache CFG negative-branch guidance kwargs (#6181) 
Signed-off-by: Yifan Zong <yzong@redhat.com>
 2026-08-22 01:22:26 +00:00
R0CKSTAR 260db8bab5 [Bugfix][Diffusion] Fix MiniMax-H3 model-level CPU offload residency (#6072) 
Signed-off-by: Xiaodong Ye <xiaodong.ye@mthreads.com>
 2026-08-21 10:30:53 +00:00
Shin 70bdd49402 [Model] Add HiDream-O1-Image support (#5194) 
Signed-off-by: yixiaoer <shin@yixiaoer.sg>
 2026-08-21 14:15:37 +08:00
MaciejBalaNVandRoger Wang 13c2de684c Cosmos3 logging and prompt improvements (#6325) 
Signed-off-by: Maciej Bala <mbala@nvidia.com>
Co-authored-by: Roger Wang <hey@rogerw.io>
 2026-08-20 12:04:49 -07:00
MaciejBalaNV b3270dec8d Cosmos3 transfer fix (#5614) 
Signed-off-by: Maciej Bala <mbala@nvidia.com>
 2026-08-20 11:40:51 -07:00
dengyunyang 8d34d3b5de [Perf][Hunyuan] Optimize for vae and patch_embed (#6306) 
Signed-off-by: dengyunyang <584797741@qq.com>
 2026-08-20 16:29:21 +00:00
linzhenpl07andClaude Opus 5 38cf9adc38 [BugFix][Diffusion] Fix MiniMax-H3 VAE hang when decoder tiles are fewer than ranks (#6345) 
Signed-off-by: linzhenpl07 <linzhenpl07@gmail.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-20 12:42:14 +08:00
Joshna-MedisettyCursorChendi.Xue
 		ea24deefcc [Bugfix][FLUX.2-klein] Fix duplicated image position ids (#6130) 
Signed-off-by: Joshna Medisetty <joshna.medisetty@intel.com>
Signed-off-by: Joshna-Medisetty <joshna.medisetty@intel.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Chendi.Xue <chendi.xue@intel.com>
 2026-08-19 16:30:12 -05:00
BruceLoveDecimaland汪志鹏 adf6d0c1ea [Model] Add SANA-WM support(Stage-1 only) (#4061) 
Signed-off-by: BruceLoveDecimal <liuqihao970610@gmail.com>
Signed-off-by: 汪志鹏 <wangzhipeng628@gmail.com>
Signed-off-by: liuqihao <liuqihao970610@gmail.com>
Co-authored-by: 汪志鹏 <wangzhipeng628@gmail.com>
 2026-08-18 23:57:55 -06:00
bjf-frzandHongsheng Liu 14bd8f8772 [REFACT]Refactor diffusion parallel state (#5531) 
Signed-off-by: bjf-frz <frz123db@gmail.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-19 11:23:10 +08:00
Canlin Guo 14f2c16fb2 [Perf] Fuse MiniMax H3 modulation with FP32 accumulation (#6281) 
Signed-off-by: Canlin Guo <canlinguosdu@gmail.com>
 2026-08-18 20:13:54 -07:00
Canlin Guo 9683b7f4b4 [Perf] Fuse MiniMax H3 SwiGLU activation (#6283) 
Signed-off-by: Canlin Guo <canlinguosdu@gmail.com>
 2026-08-18 20:12:10 -07:00
Alex Brooks b4b907e7b6 [Bugfix | Model] Fix SenseNova & Use Well-defined Model Configs (#5877) 
Signed-off-by: Alex Brooks <albrooks@redhat.com>
 2026-08-18 16:43:05 +00:00
Hongsheng Liu c3de04e127 [Bugfix] Avoid eager pi0 runtime import in pipeline registry (#6322) 
Signed-off-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-18 23:42:03 +08:00
Joshna-MedisettyHongsheng LiuCursorNick Cao
 		4cd667875f [XPU][SDXL] Fix text encoder input device under CPU offload (#6125) 
Signed-off-by: Joshna Medisetty <joshna.medisetty@intel.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Nick Cao <ncao@redhat.com>
 2026-08-18 14:03:31 +00:00
Yukim1andzwhzzz0821 0a1846aa45 [Diffusion] Add native KV cache initialization and Scheduler-managed block allocation (#6094) 
Signed-off-by: zwhzzz0821 <zwhzzz0821@users.noreply.github.com>
Co-authored-by: zwhzzz0821 <zwhzzz0821@users.noreply.github.com>
 2026-08-18 07:00:24 +00:00
TJian 170d498771 [ROCm] [CI] Fix cpu test on rocm (#6267) 
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
 2026-08-17 14:46:30 +08:00
Yichen WangandDidan Deng 2a9f6aaa8e Add π0 VLA model support (#4222) 
Signed-off-by: Yichen Wang <yichen.wang@bytedance.com>
Signed-off-by: Didan Deng <33117903+wtomin@users.noreply.github.com>
Co-authored-by: Didan Deng <33117903+wtomin@users.noreply.github.com>
 2026-08-17 14:29:17 +08:00
Hongsheng Liu 9d2bb23ff6 [Diffusion] Add loader-owned host-weight plans for DLO (TP=1) (#6213) 
Signed-off-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-16 11:02:38 +08:00
Jack Chenzhangbin.327Hongsheng Liu
 		3875f8ded4 [Core] Add realtime AR-Diffusion tick sessions for LingBot World 2.0 (#5491) 
Signed-off-by: zhangbin.327 <zhangbin.327@bytedance.com>
Signed-off-by: Jack47 <scsvip@gmail.com>
Co-authored-by: zhangbin.327 <zhangbin.327@bytedance.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-16 09:11:20 +08:00
hurukawa 2a315e1a2d [Perf] Support request-level batching for Wan2.2 pipelines (#5676) 
Signed-off-by: nagisa-kun <1434936049@qq.com>
Signed-off-by: nagisa <1434936049@qq.com>
 2026-08-15 23:58:36 +08:00
SYLARandHongsheng Liu d1e230c95b [Diffusion][Quantization] Enable MiniMax-H3 global FP8 with DLO (#5910) 
Signed-off-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-15 23:01:26 +08:00
SYLAR ce6ab0ca46 [Model] Add LTX-2.5 support (#6070) 
Signed-off-by: lishunyang12 <lishunyang12@163.com>
 2026-08-15 18:27:23 +08:00
mokekemokashliuWeiQing Chen
 		7b76b6446d [Model][Performance] Optimize MiniMax-H3 strict Ulysses boundaries (#6173) 
Signed-off-by: mokashliu <mokashliu@tencent.com>
Co-authored-by: mokashliu <mokashliu@tencent.com>
Co-authored-by: WeiQing Chen <40507679+david6666666@users.noreply.github.com>
 2026-08-15 16:27:52 +08:00
R0CKSTAR 728640f4d9 [Bugfix][MUSA][Qwen Image] Avoid complex RoPE alias guards (#6110) 
Signed-off-by: Xiaodong Ye <xiaodong.ye@mthreads.com>
 2026-08-14 15:51:23 +08:00
R0CKSTAR 022d7a7695 [Perf][Diffusion] Avoid redundant MiniMax-H3 reference video scans (#6064) 
Signed-off-by: Xiaodong Ye <xiaodong.ye@mthreads.com>
 2026-08-14 15:49:26 +08:00
Bo Lilishunyang12Claude Opus 5
 		596c16a550 [Kernel] Fuse Q/K RMSNorm and RoPE (#5990) 
Signed-off-by: Bo Li <22713281+bobboli@users.noreply.github.com>
Signed-off-by: lishunyang12 <lishunyang12@163.com>
Signed-off-by: Mengjie Zhao <zmj0129@gmail.com>
Co-authored-by: lishunyang12 <lishunyang12@163.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-14 00:46:59 +00:00
Mu GuanLin 83d1f11449 [Feat] LTX Standard Two-Stage Pipeline (#5500) 
Signed-off-by: mglyn <1203789601@qq.com>
 2026-08-14 00:13:14 +08:00
MaciejBalaNV e677360168 Add cosmos-guardrail dependency and update error message (#6107) 
Signed-off-by: Maciej Bala <mbala@nvidia.com>
 2026-08-12 17:04:07 +00:00
Wenjia LiandHongsheng Liu 38a2500bdf [Perf] MiniMax H3 Qwen3-VL support fused RMSNorm on NPU (#5915) 
Signed-off-by: Wenjia Li <wjialish@gmail.com>
Signed-off-by: Hongsheng Liu <liuhongsheng4@huawei.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-12 19:12:54 +08:00
Zhou TaichangandClaude Opus 5 2ce15ab7a0 [Rebase] Rebase to vllm 0.27.0 (#5976) 
Signed-off-by: tzhouam <tzhouam@connect.ust.hk>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-08-11 15:23:46 +00:00
Jerry Song 89015d5cad [Feature]: Adds distilled LoRA support for diffusion models (#2783) 
Signed-off-by: Songrui625 <songrui625@gmail.com>
 2026-08-11 14:23:43 +00:00
KristofferDidan DengHongsheng Liu
 		4ab1b4ff9c [Perf][Flux2][HunyuanVideo1.5] Skip attention-mask to avoid varlen path (#4645) 
Signed-off-by: kTorp <Kristoffer.Torp@amd.com>
Signed-off-by: Didan Deng <33117903+wtomin@users.noreply.github.com>
Co-authored-by: Didan Deng <33117903+wtomin@users.noreply.github.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-11 15:31:02 +08:00
WeiyanDidan DengHongsheng Liu
 		06e733d3cd [Model] Add LongCat-Video-Avatar-1.5 ai2v, at2v support (#4099) 
Signed-off-by: weiyan <weiyanlin117@gmail.com>
Signed-off-by: Didan Deng <33117903+wtomin@users.noreply.github.com>
Co-authored-by: Didan Deng <33117903+wtomin@users.noreply.github.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
 2026-08-11 15:17:17 +08:00
Zijun HuangandWeiQing Chen 1a56953d7a [NPU][Model] Add distilled 4-step sigma schedule support for MiniMax H3 t2va (#5991) 
Signed-off-by: Zijun Huang <zijunhua@usc.edu>
Co-authored-by: WeiQing Chen <40507679+david6666666@users.noreply.github.com>
 2026-08-11 13:46:10 +08:00
WeiQing Chen 1f65814fab [CI] Align MiniMax H3 Ref2VA inputs and add I2VA/Ref2VA accuracy coverage (#5978) 
Signed-off-by: david6666666 <530634352@qq.com>
 2026-08-11 13:36:37 +08:00
ooooooye 740f45abcd [Perf][Diffusion] MiniMax-H3: opt into packed varlen attention on NPU to eliminate quadratic mask materialization (#5891) 
Signed-off-by: brandneway <gyuan4892@gmail.com>
 2026-08-10 19:47:03 +08:00
R0CKSTAR 636d44e272 [Perf][MUSA] Restore MiniMax-H3 dynamic RoPE fusion (#5881) 
Signed-off-by: Xiaodong Ye <xiaodong.ye@mthreads.com>
 2026-08-10 17:24:46 +08:00