 bjf-frz
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2447740308
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[Perf]perf: skip unused Cosmos3 I2V conditioning latents (#4614)
Signed-off-by: bjf-frz <frz123db@gmail.com>
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2026-06-22 09:51:47 +00:00 |
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汪志鹏
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a10eac0f8c
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[Feature]: Migrate magi human example (#4572)
Signed-off-by: princepride <wangzhipeng628@gmail.com>
Signed-off-by: 汪志鹏 <wangzhipeng628@gmail.com>
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2026-06-22 15:17:00 +08:00 |
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WeiQing ChenandHongsheng Liu
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f0d7fe18f2
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[Perf][Cosmos3] Optimize I2V conditioning transfer (8.63% faster x-inference) (#4467)
Signed-off-by: david6666666 <530634352@qq.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-22 01:59:03 +00:00 |
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Alex Brooksand汪志鹏
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7ff11d8d0f
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[Perf/Fix] Reimplement Batched CFG Forward for Bagel (#4098)
Signed-off-by: Alex Brooks <albrooks@redhat.com>
Co-authored-by: 汪志鹏 <wangzhipeng628@gmail.com>
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2026-06-22 07:37:21 +08:00 |
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MaciejBalaNVandHongsheng Liu
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fc32d9fe6f
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Improve Cosmos3 v2v quality (#4514)
Signed-off-by: Maciej Bala <mbala@nvidia.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-21 22:20:30 +08:00 |
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MaciejBalaNV
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a1e1ac0155
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Cosmos3 transfer (#4379)
Signed-off-by: Maciej Bala <mbala@nvidia.com>
Signed-off-by: MaciejBalaNV <mbala@nvidia.com>
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2026-06-21 09:59:18 +08:00 |
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Zhengyuan Su (苏政渊)andClaude Opus 4.8
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2d0b1d8a29
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[Diffusion] add GR00T-N1.7 pipeline with OpenPI serving (#3798)
Signed-off-by: Zhengyuan Su <su.zhengyuan@u.nus.edu>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-06-20 11:45:26 +08:00 |
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Alex Brooks
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6ff246bf3c
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[Cache Refactor 1/N] Simplify CacheDiT Integration (#2527)
Signed-off-by: Alex Brooks <albrooks@redhat.com>
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2026-06-20 08:30:44 +08:00 |
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amy-why-3459
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f05e03aea8
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[Perf][DreamZero]dreamzero supports CUDA graph, torch.compile, and DiT Caching. (#4213)
Signed-off-by: amy-why-3459 <wuhaiyan17@huawei.com>
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2026-06-19 14:24:37 +08:00 |
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yangyonggit
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37a442447e
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[Cleanup] Remove duplicate HiDreamI1ImagePipeline (fixes #4009) (#4045)
Signed-off-by: leo.yang <leo.yang.engineer@gmail.com>
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2026-06-19 06:32:18 +08:00 |
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Honghan Zhu
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8f28b969e9
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[Feat] DreamZero fix tp & cross attn cache (#4154)
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2026-06-18 10:57:04 +00:00 |
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f75c437a60
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[Refactor]Base class for dit pipelines with unified parameter declaration[1/N] (#4225)
Signed-off-by: princepride <wangzhipeng628@gmail.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
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2026-06-18 17:14:18 +08:00 |
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汪志鹏
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f195e44bc1
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[BugFix]: Fix Bagel generate_image denoising schedule (#4509)
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2026-06-18 02:02:38 +00:00 |
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Nick CaoandClaude
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e957d16f8d
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[Refactor] Migrate existing pipelines to use SupportsComponentDiscovery for offload discovery (#3076)
Signed-off-by: Nick Cao <ncao@redhat.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-06-17 21:33:06 +08:00 |
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KristofferandHongsheng Liu
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890803ca06
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[Wan2.2] Fix "uninitialized nn.Module of type RotaryEmbeddingWan" graph-break (#4053)
Signed-off-by: Kristoffer Torp <kristoffer.torp@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-17 15:48:22 +08:00 |
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KristofferandHongsheng Liu
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e3621ec633
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[Perf][qwen-image-edit] Skip attention-mask to avoid varlen path (#4293)
Signed-off-by: kTorp <Kristoffer.Torp@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-16 22:52:04 +08:00 |
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Chendi.XueandHongsheng Liu
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e7f0db1067
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[SDXL] SDXL model enabling (#4331)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-16 22:51:11 +08:00 |
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Samit
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5f5b77aa9c
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[BugFix][Qwen-Image] align txt_seq_lens RoPE width with padded embeds (#4474)
Signed-off-by: samithuang <285365963@qq.com>
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2026-06-16 19:09:25 +08:00 |
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Kwokho TsuiandKwokho
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3bce5e2e3a
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[Bugfix] Cosmos3: fix HSDP dtype mismatch on time_embedder via _hsdp_ignored_modules (#4452)
Signed-off-by: Kwokho <kh_tsui@163.com>
Co-authored-by: Kwokho <kh_tsui@163.com>
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2026-06-16 04:06:14 +00:00 |
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46e0b71423
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[Enhancement] Introduce High-Performance MoT (Mixture-of-Tokens) Kernels: Triton Implementation (#3960)
Signed-off-by: Yufeng Zhu <yzhu802@gatech.edu>
Signed-off-by: 汪志鹏 <wangzhipeng628@gmail.com>
Signed-off-by: princepride <wangzhipeng628@gmail.com>
Signed-off-by: Zhengyuan Su <su.zhengyuan@u.nus.edu>
Co-authored-by: Yufeng Zhu <yzhu802@gatech.edu>
Co-authored-by: Zhengyuan Su <su.zhengyuan@u.nus.edu>
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-06-16 03:08:02 +00:00 |
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dengyunyang
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a86c333c7e
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[Perf][HunyuanImage] remove sync logic (#4401)
Signed-off-by: dengyunyang <584797741@qq.com>
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2026-06-16 05:28:51 +08:00 |
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Yuzhu Dong
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e2e79177db
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Support DROID policy server for Cosmos3 OpenPI (#4282)
Signed-off-by: yuzhud <yuzhudong@gmail.com>
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2026-06-15 21:22:59 +08:00 |
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ae937320ff
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[Feature] Add HunyuanImage3 DiT grouped step batching (#4041)
Signed-off-by: TaffyOfficial <2324465096@qq.com>
Signed-off-by: zuiho <2324465096@qq.com>
Co-authored-by: TaffyOfficial <2324465096@qq.com>
Co-authored-by: Gao Han <hgaoaf@connect.ust.hk>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-15 20:36:41 +08:00 |
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Mu GuanLin
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11829ccd75
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[Bugfix] Fix LTX-2.3 tensor-parallel gated attention (#4439)
Signed-off-by: mglyn <1203789601@qq.com>
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2026-06-15 11:40:06 +00:00 |
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Ting FU
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6c6fde3e6d
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[BugFix] Fix HunyuanImage3 size match issue (#4416)
Signed-off-by: Semmer <semmer@live.cn>
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2026-06-15 09:36:39 +08:00 |
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Zhou Taichang
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7b837944a1
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[Rebase] Rebase to vllm 0.23.0 (#4286)
Signed-off-by: tzhouam <tzhouam@connect.ust.hk>
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2026-06-13 16:43:02 +00:00 |
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Chendi.Xue
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a9ee92ddec
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[XPU] update Dreamzero to support any HW (#4399)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
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2026-06-13 15:32:39 +00:00 |
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Joni JuvonenandHongsheng Liu
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20b7a67b0d
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[Perf][Wan2.2] Skip attention mask for zero-padded SP sequences to avoid varlen path (#3763)
Signed-off-by: jjuvonen-amd <joni.juvonen@amd.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-13 07:50:39 +08:00 |
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Ting FU
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1be1a71156
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[Model] Add more resolution support for HunyuanImage3.0 (#4004)
Signed-off-by: Semmer <semmer@live.cn>
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2026-06-12 14:44:00 +08:00 |
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Chendi.Xue
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3fe3aa359b
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[XPU][COSMOS3] removing cuda hardcode and make VLLM_VIDEO_SYNC_TIMEOUT a tunable config (#4360)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
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2026-06-12 04:55:07 +00:00 |
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MaciejBalaNVandHongsheng Liu
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03cc888485
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[refactor] Refactor guardrail error handling - add 400 error code (#4297)
Signed-off-by: Maciej Bala <mbala@nvidia.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-11 21:09:24 +00:00 |
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dengyunyang
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eb964dcec5
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[HunyuanImage][Perf] opt prepare_attention_mask for e2e latency 6% reduction (#4333)
Signed-off-by: dengyunyang <584797741@qq.com>
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2026-06-11 19:06:22 +08:00 |
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Chendi.XueandHongsheng Liu
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5414f78e5f
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[WAN2.2-S2V] Add server API for image + audio (#3394)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-11 18:50:03 +08:00 |
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WeiQing ChenandHongsheng Liu
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f3d40b5402
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[Bugfix] Add Cosmos3-Nano baselines and fix USP gather (#4301)
Signed-off-by: david6666666 <530634352@qq.com>
Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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2026-06-11 18:36:26 +08:00 |
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Kushanam
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74b5ae5ebe
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[Bugfix] Fix SP denoise indentation bug on BAGEL (#4328)
Signed-off-by: Kushan A. <kahmadian@nvidia.com>
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2026-06-11 03:32:22 +00:00 |
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3753b21c3d
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[Feature] LoRA support for SenseNova-U1 (#3971)
Signed-off-by: leohuang257 <masugchds@gmail.com>
Signed-off-by: Guanzhe (Leo) Huang <116847811+leohuang257@users.noreply.github.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Yuanheng Zhao <54058983+yuanheng-zhao@users.noreply.github.com>
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2026-06-09 14:36:35 +00:00 |
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Mu GuanLin
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bf03413c36
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[Feat] Add vae-decode-parallel for LTX-2.3 (#4277)
Signed-off-by: mglyn <1203789601@qq.com>
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2026-06-09 13:14:16 +00:00 |
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Mu GuanLin
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02eb7a4ecb
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[Bugfix] Register LTX RMSNorm identity weight as buffer (#4278)
Signed-off-by: mglyn <1203789601@qq.com>
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2026-06-09 09:09:39 +00:00 |
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yangjianjuan
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cb1c5a0c39
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[Perf] lance perf optimize (t2i & i2i) (#4214)
Signed-off-by: yangjianjuan <510818155@qq.com>
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2026-06-09 08:31:57 +00:00 |
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weizhoublue
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1b85df0510
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fix: Propagate Quantization Configuration to HunyuanVideo-1.5 I2V Transformer to Enable FP8 Layers (#4245)
Signed-off-by: weizhoublue <weizhou.lan@daocloud.io>
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2026-06-09 15:28:32 +08:00 |
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MaciejBalaNV
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2f25195750
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Cosmos3 video to video generation (#4266)
Signed-off-by: Maciej Bala <mbala@nvidia.com>
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2026-06-09 03:04:05 +08:00 |
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Mu GuanLin
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13f9ecaef8
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[Perf] Keep LTX2.3 auxiliary modules resident by default (#4144)
Signed-off-by: mglyn <1203789601@qq.com>
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2026-06-08 19:15:06 +08:00 |
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SYLAR
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29b18ea298
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[Quant] ModelOpt FP8 for Wan2.2 & HunyuanVideo-1.5 video-gen (#3305)
Signed-off-by: WeiQing Chen <david6666666@users.noreply.github.com>
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2026-06-08 02:53:06 +08:00 |
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Gao Han
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963ba1ab7a
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[CI] Revert "[Feature] gen-only FP8 Quantization Support for SenseNova-U1" (#4196)
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2026-06-06 08:39:10 +08:00 |
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Jianbao Huang
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6cefe91370
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[Perf] Enable fused RMSNorm for HunyuanImage3 (#3959)
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2026-06-05 07:41:56 +00:00 |
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Yaegaki1Erikaandreandeng
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84569280b1
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[Bugfix]Fix HunyuanImage3 conditional image and prompt kwargs alignment (#4145)
Signed-off-by: reandeng <reandeng@tencent.com>
Signed-off-by: Yaegaki1Erika <70182590+Yaegaki1Erika@users.noreply.github.com>
Co-authored-by: reandeng <reandeng@tencent.com>
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2026-06-05 12:47:25 +08:00 |
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Guanzhe (Leo) Huang
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b63b36ded3
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[Feature] gen-only FP8 Quantization Support for SenseNova-U1 (#3943)
Signed-off-by: leohuang257 <masugchds@gmail.com>
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2026-06-05 02:51:11 +00:00 |
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Chendi.XueandMengkejiergeli Ba
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31f882935d
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[XPU][S2V] Optimize Wan2.2 S2V: RoPE refactor + cache_dit enabling (#4062)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Co-authored-by: Mengkejiergeli Ba <mengkejiergeli.ba@intel.com>
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2026-06-05 06:20:16 +08:00 |
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dengyunyang
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469c1dc87e
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[HunyuanImage3.0][Performance][Optimazation]Adjust perf config (#4149)
Signed-off-by: dengyunyang <584797741@qq.com>
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2026-06-04 22:54:46 +08:00 |
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Alex Brooks
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e10aca30ec
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[CI] Update Bagel Pixels (#4081)
Signed-off-by: Alex Brooks <albrooks@redhat.com>
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2026-06-04 10:37:34 +00:00 |
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