Update device-model matrix with Qualcomm TTS component evidence

docs/design/omni_edge_e2e_roadmap.md

@@ -15,7 +15,9 @@ remain open; the 2026-09-22 audit remains the historical baseline.
 
 The [Spark hosted Qualcomm component expansion](../../benchmarks/edge_harness/results/e2e_expansion_20260923/evidence/spark_s24_full_attention/README.md) advances M1 only to one real fixed-shape decoder attention layer. The same W8A16 QNN DLC ran on S24, Snapdragon X Elite CRD and SA8775P ADP NPUs with identical outputs on one pinned fixture; S25 had prior separate component evidence. On [RB3 Gen 2](../../benchmarks/edge_harness/results/e2e_expansion_20260923/evidence/spark_rb3_full_attention/README.md), the tested W8A16 graph failed QNN loading even after an exact-device compile. FP32 ONNX ran on CPU with near-source parity, while calibrated W8A8 ran on NPU but had 20.9% hidden-state relative L2 and remains numerically unqualified. These are component C results, not full M1: device-local 28-layer prefill/continuous decode, KV/ring, sampling, token quality, admission/cancellation, complete-request timing and sustained power/thermal gates remain open. AI Hub is the test facility, not a deployment dependency.
 
-The [Qwen3-TTS Code2Wav Qualcomm follow-up](../../benchmarks/edge_harness/results/e2e_expansion_20260924/evidence/qwen_tts_vocoder_qualcomm/README.md) adds a retained same-fixture numerical check to M2. A fresh SA8775P GPU-requested output saturated 96.63% of samples and differs from original ONNX CPU by 11.832 relative L2, so the tested vocoder target fails the numerical gate despite historical component profiling. Historical SA8775P and RB3 vocoder profiles have mixed CPU/GPU placement; their estimated-time fields were minima. X Elite ONNX compile passed, while RB3/X Elite runtime and SA control jobs remained pending at this snapshot. M2 still requires a quality-passing talker/predictor/vocoder set, device-local co-residency and handoff, playable streaming and sustained memory/power validation.
+The [Qwen3-TTS Code2Wav Qualcomm follow-up](../../benchmarks/edge_harness/results/e2e_expansion_20260924/evidence/qwen_tts_vocoder_qualcomm/README.md) adds a retained same-fixture numerical check to M2. A fresh SA8775P GPU-requested output saturated 96.63% of samples and differs from original ONNX CPU by 11.832 relative L2, so the tested vocoder target fails the numerical gate despite historical component profiling. Historical SA8775P and RB3 vocoder profiles have mixed CPU/GPU placement; their estimated-time fields were minima. RB3 TFLite GPU-requested inference returned an unsaturated but 15.73%-relative-L2 divergent waveform; its fresh profile was pending. X Elite ONNX CPU inference matched the local ONNX Runtime output with 8.09e-7 relative L2, while its profile, DirectML retry and SA controls remained pending. M2 still requires a quality-passing talker/predictor/vocoder set, device-local co-residency and handoff, playable streaming and sustained memory/power validation.
+
+A separate [28-layer talker decode-step attempt](../../benchmarks/edge_harness/results/e2e_expansion_20260924/evidence/qwen_tts_talker_qualcomm/README.md) retains a synthetic fixed-cache fixture and CPU reference. Historical FP16 QNN context-binary compiles passed for S24, S25, SA8775P and X Elite; their same-fixture NPU inference was pending at this snapshot. RB3 rejected that floating-point-input artifact. None advances M2 to numerical talker or full-stream qualification yet.
 
 The [WSL CPU expansion](../../benchmarks/edge_harness/results/e2e_expansion_20260923/README.md)
 adds constrained three-stage MiniCPM-o text-to-speech requests and a CPU-only