Enable scoped Qwen3.8 Omni inference and CPU TTS compatibility
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@@ -4,7 +4,7 @@ from typing import NamedTuple
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import pytest
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import torch
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from vllm_omni.core.prefix_cache import OmniTensorPrefixCache
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from vllm_omni.core.prefix_cache import OmniTensorPrefixCache, _PendingAsyncWrite
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pytestmark = [pytest.mark.core_model, pytest.mark.cpu]
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@@ -163,6 +163,40 @@ def test_update_no_multimodal():
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assert torch.all(slot_states == new_states)
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def test_pending_write_skips_vllm_unmapped_slot_sentinel():
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class CompletedEvent:
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def synchronize(self):
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pass
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cache = get_omni_pcache_with_mm_tensors({"vision": HIDDEN_SIZE}, seq_len=3)
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cache._pending_write = _PendingAsyncWrite(
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event=CompletedEvent(),
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num_tokens=3,
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slots_cpu=torch.tensor([8, -1, 9], dtype=torch.int32),
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hidden_cpu=torch.tensor([[1.0, 1.0], [99.0, 99.0], [2.0, 2.0]]),
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mm_cpu={"vision": torch.tensor([[3.0, 3.0], [99.0, 99.0], [4.0, 4.0]])},
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)
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cache._consume_pending_write()
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assert cache._pending_write is None
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assert cache.hidden_states_cache.view(-1, HIDDEN_SIZE)[8:10].tolist() == [[1.0, 1.0], [2.0, 2.0]]
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assert cache.mm_outputs_cache["vision"].view(-1, HIDDEN_SIZE)[8:10].tolist() == [[3.0, 3.0], [4.0, 4.0]]
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def test_synchronous_write_skips_vllm_unmapped_slot_sentinel():
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cache = get_omni_pcache_with_mm_tensors({"vision": HIDDEN_SIZE}, seq_len=3)
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cache.update_omni_tensor_prefix_cache(
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hidden_states=torch.tensor([[1.0, 1.0], [99.0, 99.0], [2.0, 2.0]]),
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multimodal_outputs={"vision": torch.tensor([[3.0, 3.0], [99.0, 99.0], [4.0, 4.0]])},
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num_tokens_unpadded=3,
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slot_mapping=torch.tensor([8, -1, 9], dtype=torch.int32),
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)
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assert cache.hidden_states_cache.view(-1, HIDDEN_SIZE)[8:10].tolist() == [[1.0, 1.0], [2.0, 2.0]]
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assert cache.mm_outputs_cache["vision"].view(-1, HIDDEN_SIZE)[8:10].tolist() == [[3.0, 3.0], [4.0, 4.0]]
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def test_update_uses_precomputed_hidden_states_cpu():
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"""Precomputed CPU staging should be the only hidden-state cache source."""
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cache = get_omni_pcache()
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