[Model][Frontend] MiniMax-H3: Add opt-in planar video response encoding (#6288)
Signed-off-by: MosCloud <bwzhang1991@163.com> Co-authored-by: Hongsheng Liu <liuhongsheng4@huawei.com>
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@@ -65,6 +65,31 @@ On AMD ROCm, install without the `[fa4]` extra (FA4 is CUDA-only) and use
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`ffmpeg` and `ffprobe` must be available on `PATH`. They are used for
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reference-video preparation and MP4 output.
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## CPU MP4 response encoding
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For CUDA and ROCm deployments, non-streaming MP4 responses are encoded on the
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host CPU through PyAV/libx264 after generation. The response encoder selects the
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path automatically at runtime: inputs with a supported frame shape, common dtype,
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and RGB per-channel contiguous layout use direct planar frames; other inputs
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fall back to the legacy path before the PyAV container is opened. No CLI flag,
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model declaration, or user configuration is required. Streaming fMP4 output is
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unchanged.
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A community benchmark on 2x Xeon 8480C reported the following comparison
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between the legacy and direct planar paths
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([full result](https://github.com/vllm-project/vllm-omni/pull/6288#issuecomment-5337546499)):
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| Metric | Legacy | Direct planar | Change |
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|---|---:|---:|---:|
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| Median wall time | 1.805 s | 1.394 s | -22.8% |
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| Median process CPU time | 3.613 s | 3.207 s | -11.2% |
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| Peak RSS | 3182 MiB | 2794 MiB | -387 MiB (-12.2%) |
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Across the 1.0-8.7 s sweep, wall-time improvement was approximately 21.8-22.6%;
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outputs were byte-identical and full decode passed. This is evidence for host
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CPU response encoding. Actual gains depend on the CPU and runtime, and should
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not be interpreted as GPU, DiT, or stage 0 speedups.
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## Start a server
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Pass the repository ID directly. The pipeline uses `FL2VA` for model discovery
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